How does my SoC access FPGA IP Cores ??

[ThangND]

Hi,

I'm using Altera Cyclone V SoC, and I'm trying to access FPGA sides (the IP cores, for example, the FIFOed Avalon Uart IP Core). In NIOS II, the IP cores use the Altera HAL drivers included in the package, however, the drivers work with HAL library for NIOS II Systems. My question is: 

1) How can I access the FIFOed Avalon UART IP Core from my SoC ?? Can I work with the included Altera HAL drivers of the IP and just edit some parts in the drivers ?? 

2) In case it's difficult, can I use another UART IP Core, such as the Altera 16550 UART Ip Core, to make things easier ?? What is the best way to access the UART IP Core in FPGA sides, as I don't want to use the UART peripherals of the SoC ??

[sstrell]

You should probably start here:

https://www.intel.com/content/www/us/en/programmable/support/training/course/osoc2000.html

The flow for SoC devices is an Arm flow, which is quite different from Nios if that's what you're familiar with (though the .sopcinfo file is key for both).

[AnilErinch_A_Intel]

Hi Duc Thang,

The communication to the FPGA side peripherals from the HPS is achieved through the use of bridges.

You can see the below link for a UART IP access methods.

https://forum.rocketboards.org/t/from-hps-how-to-sending-and-receive-from-fpga-uart-altera-uart-qsys-ip/995/8

Also the video below talks more about the bridges.

https://www.youtube.com/watch?v=RTmDgNXIwKQ

Thanks and Regards

Anil