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How does the ADC I/O on Cyclone V GX Starter Kit Work?`

Altera_Forum
Honored Contributor II
945 Views

I used the system builder and it generated the Verilog I/O as follows: 

 

//////////// ADC SPI ////////// 

output ADC_CONVST, 

output ADC_SCK, 

output ADC_SDI, 

input ADC_SDO, 

 

I read the LTC2308 and I am confused on how these registers work in relation to the ADC. According to the datasheet, the ADC_CONVST initiates the data conversion, so wouldn't it be an input? The data sheet also called SCK and SDI as inputs and SD0 as outputs.  

 

I think I'm fundementally thinking about it in the wrong way.
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Altera_Forum
Honored Contributor II
130 Views

 

--- Quote Start ---  

I used the system builder and it generated the Verilog I/O as follows: 

 

//////////// ADC SPI ////////// 

output ADC_CONVST, 

output ADC_SCK, 

output ADC_SDI, 

input ADC_SDO, 

 

I read the LTC2308 and I am confused on how these registers work in relation to the ADC. According to the datasheet, the ADC_CONVST initiates the data conversion, so wouldn't it be an input? The data sheet also called SCK and SDI as inputs and SD0 as outputs.  

 

I think I'm fundementally thinking about it in the wrong way. 

--- Quote End ---  

 

 

It is input pin to the LTC2308 CONVST Pin, which is controlled by the FPGA device. So it is the FPGA output signals to the LTC controlling. It is the same reason to SDI & SCK Pin, both of them are be configures as output pin to the FPGA device.  

 

It is output pin to the LTC 2308 SDO, the signal is output from LTC to FPGA for the data receiving, so it is FPGA input pin. 

In the system builder, the pin assignments are all correct.
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