Hi, we are exploring Arria 10 Partial Reconfiguration over PCIe and are concerned how much device space will be "wasted" in single region Partial Reconfiguration comparing to the same design without using any Partial Reconfiguration. Can Intel provide such info as, for example, percentage of logic fabrics "wasted" that can be otherwise used for logic if not for partial reconfiguration? I understand that it is design dependent, but would appreciate it if Intel has some spread sheet to show some statistical results, or if not, some range of percentage. Thanks.
You can set the Logic Lock placement and routing regions to whatever size you want, so you can size them to *just* fit the largest persona for your PR region logic if you want though that doesn't give you room to grow.
PR does add wire LUTs (logic stubs essentially; just a few gates) at all the I/O ports of the PR region, so the more I/O to the region, the more wire LUTs required.
Check out the online training (and its related trainings) for more details: