Hi,I just got my Cyclone III development kit. However, it seems the examples does not have all features demonstrated. In all examples, only one DDR2 chip (16bit) is accessed even there are at least 2 chips (32bit on DDR2_Bottom, 40bit on DDR2_Top). I am trying to modify the standard example to use 32 bit(2 chips) access. I modified the memory interface DQ width from 16 to 32. However the compiler generates some strange error: >>Error: On-chip termination Control Block "termination_blk0" driven by Rup or Rdn pin "termination_blk0~_rup_pad" with non-matching side location constraints for the output or bidir pins driven by the block My questions are: 1. Is it the right approach (changing DQ with in DDR2 controller) to enable 32bits access? 2. How can I fix the error? what does the error message mean? 3. Is there any CycloneIII development kit reference design that already accesses DDR2 (either top or bottom) with 32 bit DQ width? Thanks, GL888
Hi,I did more test trying to use the other memory chips not used in reference design (for example, U25A in DDR2_BOTTOM). I switched DQ width back to 16 and make the following pin assignment modifications. mem_dm[1..0] <= ddr_dm[3..2] mem_dq[15..0] <= ddr_dq[31..16] mem_dqs[1..0] <= ddr_dqs[3..2] The same error (shown in earlier message) will show up. Once I switched back to the original chip (U26A) by assigning mem_dm[1..0] <= ddr_dm[1..0] mem_dq[15..0] <= ddr_dq[15..0] mem_dqs[1..0] <= ddr_dqs[1..0], then every is fine. What is problem when memory chip U25A is used? Thanks, gl888
After regenerating in SOPC Builder with a wider data width make sure to run the DDR SDRAM pin assignments .tcl file. The example designs in their current state would only have x16 interfaces constrained and not the extra pins you are adding.