Hello, I am using Quartus Prime Lite Edition to programm a MAX10 (10M08SAU169C8G). I wanted to add a ROM which is initialized with a .mif File. The design compiles and ROM works fine on the FPGA. I am also able to simulate the design.
Only problem: The ROM's output is not as excepted. Appearently only every sixteenth values is correct. All other output are 0x00.
Attached you find the rom and the testbench to recreate the problem.
Your ROM design is not having a write-enable(wren) signal?
The test bench is not correct, You have to consider read and write latency.
After giving address waiting for at least 2 clock cycles for read or write from the memory.
For example, you can refer below project which can be run using do,do file or testbench.do file.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.