How to Visualize the i2c bus of the gsensor example with a logic analyser ( DE10 Standard FPGA)

[Lionel_10]

I would like to Visualize the i2c bus of the gsensor example with a logic analyser. But we cannot use the LTC connector pins because it’s related to I2C2 while in our example it is related to the i2c1 bus.

Sincerely,

[EricMunYew_C_Intel]

You may integrate the SignalTAP II logic analyzer in your design to monitor internally the i2c bus.

https://www.intel.com/content/www/us/en/docs/programmable/683552/18-1/design-debugging-with-the-logic-analyzer-69524.html