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Altera_Forum
Honored Contributor I
1,096 Views

How to access SRAM on CycloneIII dev kit - not via nios !

Hi, 

 

I've been searching the forums for quite some time, and couldn't find an answer to my problem. 

 

I'm trying to access the ssram on the CycloneIII Starter kit board. however, from the SSRAM data sheet, it is supposed to work in bursts. latch the starting address and then use the ADV pin to increment it internally. 

 

unfortunately, on the board, most of the control pins are ties to GND or VCC. to ADV, ADSP_N and such are not in use. 

 

how do I simply write a stream of data+addresses+valid strobe into the memory ? 

 

I tried building a simple counter, to act as both address bus and data bus. so basically, the RAM should be filled by : 0,1,2,3,4,5,6,... etc. 

 

but when I try to read, I'm getting 3,3,3,3,7,7,7,7,11,11,11,11 

 

I'm guessing I'm either mixing the signals or the ssram is useless as a random access memory without the burst mode. 

 

can someone provide a sequence (pseudo code, or verilog/VHDL) that will help me take a 60MHz byte stream (byte per clk) and store it in the ssram. 

 

then read the ssram content at 50MHz (32 bits per clk) 

 

withput the use of the burst mode (that is not available on the dev kit) ? 

 

 

thanks  

 

Raanan
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5 Replies
Altera_Forum
Honored Contributor I
61 Views

Hi, 

never used the SSRAM on that kit but it should be possible. 

 

First, on that board, the SSRAM data pins are shared with the Flash data pins. 

Make sure Flash is in high-Z. 

 

Second, since some of the control signals are hardwired, that probably means you can only use a subset of the SSRAM chips operating modes. 

So, you need to take a look at the state of each hardwired signal and see what modes you can still use. 

You may find that either 

a) you can't use burst mode 

b) you must use (some) burst mode 

 

Lastly, your requirement (60 MHz 8bit write, 50 MHz 32bit write) is tricky.  

Start by getting the SSRAM to work in a simpler 50 MHz 32 bit write, 32 bit read mode.
Altera_Forum
Honored Contributor I
61 Views

thank you for the reply. 

 

let me rephrase the issue. 

I don't want to write and read simultaneously. it's filling the memory first, and then read it. 

 

I'm trying to use the test code: 

///////////////////////////////////////////// 

always @(posedge osc_clk or negedge reset_n) 

if (~reset_n) begin 

ram_cnt <= 0; 

end 

else begin 

ram_cnt <= ram_cnt + 1; 

end 

 

assign ssram_adsc_n = 1'b0; 

assign ssram_ce_n = 1'b0; 

assign flash_ssram_a = ram_cnt[9:1]; 

assign ssram_bwe_n = ram_cnt[10]; 

assign ssram_oe_n = ~ram_cnt[10]; 

assign flash_ssram_d = (ssram_oe_n) ? ram_cnt[9:1] : 32'bZ; 

/////////////////////////////////////////////  

 

the code should simply fill each address with a consecutive number. 

however, although the write sequence is 0,1,2,3,4,5,6,7,8,9,10,11 (inc per clk). I see that on the output the data lines show -1,-1,-1,-1,3,3,3,3,7,7,7,7,9,9,9,9,11,11,11,11 etc. 

 

all I need is an example of code (Verilog or VHDL, not C) that will allow writing of a streaming data (60MHz, if it is relevant) into the SSRAM. and an example of how to read it in a stream after than. 

 

thanks
Altera_Forum
Honored Contributor I
61 Views

I think you are writing 32bit data with byte addressing, then you write four times on the same physical address (e.g. 0,1,2,3 all are written to address 0, then 4,5,6,7 all to address 4 and so on). When using 32bit accesses, addresses must be multiples of 4. 

 

I think you simply have to discard two lower bits of flash_ssram_a: 

assign flash_ssram_a[10:2] = ram_cnt[9:1];
Altera_Forum
Honored Contributor I
61 Views

Genius ! 

works perfectly. 

 

if it was possible, I'd sent you a virtual beer :)
Altera_Forum
Honored Contributor I
61 Views

 

--- Quote Start ---  

 

if it was possible, I'd sent you a virtual beer :) 

--- Quote End ---  

 

If you like, you can possibly award reputation points, 

although I'd rather have appreciated the beer mostly ;)
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