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XG_Kang
Novice
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How to assign LVDS in 1.8V bank in Cyclone VE

How to assign A LVDS clock to CLKn pins in 1.8V IO Bank in 5CEA9 device。If the LVDS clock signal name is clk1_p/clk1_n,it can be assigned to GCLK pins , but how to assign the IO Standard? All other signals in the same IO Bank is 1.8V, if LVDS IO standard is assigned to clk1_p/clk1_n, they are confilted to IO standard of other signals in the same IO bank.

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3 Replies
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In cyclone V, 1.8V IO bank is not support the LVDS IO standard.Can you refer the datasheet (below link) table 20. for the VCCIO requirement for the LVDS.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51002.pdf.

 

In general assign the LVDS std to the clk pins in few ways

i) Use the pin planner setting in the quartus -> Assignments->Pin planner -> dropdown menu to assign the IO standrads,

ii) using Tcl assignment in qsf file, for example

set_instance_assignment -name IO_STANDARD "LVDS" -to "net_name_to assign(p)" 

set_instance_assignment -name IO_STANDARD "LVDS" -to "net_name_to_assign(n)"

 

Thanks ,

 

Regards,

Sree

XG_Kang
Novice
75 Views

Thanks.

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Can you close the case ?

 

Thank you ,

 

Regards,

Sree

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