I found a demo DE0_NANO_SDRAM_Nios_Test from this topic: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Can-t-get-DE0-nano-board-to-boot-from-EPCS-with-NIOSII-code/td-p/698479 , which is provided by Intel, based onn Intel descrption, the nios ii code runs from SDRAM (not on-chip memory) .
I had two questions when running this demo:
1. I used Quartus lite v18.1, I tried to download the .elf file, but got the error shown in this screenshot, how this happened? I used wrong Quartus?
2. Is it possible to add the .elf to .sof, then convert .sof to .jic? If yes, how to do it?
I know how to add the .elf to .sof then convert .sof to .jic for the project that nios code run on on-chip memory, but I don't know how to do it for the project that nios code run on SDRAM.
Thanks in advance, hope someone can help me.
=> pls follow bellow video for combining the .elf into .sof file.
=> .sof to ,jic file converting process document sharing here
if you have any doubts or any issues in this process let me.
Thanks for your advice.
My first demo which the nios ii code runs on on-chip memoy: I followed the steps in the video, combined the .elf into .sof, convert it to .jic, and run successfully without problem.
However, the second demo(DE0_NANO_SDRAM_Nios_Test provided by Intel) which the nios ii code runs on external SDRAM memory: I tried to follow the steps, in the SDRAM contoller of the qsys system, I can't find the two options to check in the "Memory Initialization", as shown in this screenshot, do you have any idea?
Actually the design is provided by Intel as I said in my first thread, this is the original source: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Can-t-get-DE0-nano-board-to-boot-from-EPCS-with-NIOSII-code/td-p/698479
And I opened the design with Quartus lite v18.1, I can see the SDRAM controller without any problem.
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