I am a new learner of FPGA and designing a FPGA hardware using Cyclone 10 LP. If I want to load the .jic to EPCS16 using JTAG, is it needed to connete the MSEL[3..0] as 0010? The handbook suggests the MSEL pins should be connected to VCCA(2.5V) or GND, but the configuration voltage standard is 3.3/3.0. So are they(2.5V and 3.3V) all OK for MSEL pins?
My VCCIO is 3.3V and VCCA is 2.5V.
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I have checked, the MSEL pins are require to be hardwire the MSEL pins to VCCA (2.5V) or GND without pull-up or pull-down resistors. This has been clearly stated in the Cyclone 10 LP device handbook. Please do not be confuse between configuration voltage standard (for example 3.3V/3.0V) and the MSEL pin connection to VCCA. The configuration voltage standard refers to the voltage level applied to the VCCIO supply of the bank in which the configuration pins reside in.
I came across this old post and I actually have a related question. The configuration pins are split between 4 banks in the Cyclone 10 LP, namely banks 1, 5, 6 and 8.
What happens if different VCCIO voltages are applied to those banks? For example, let's say banks 5 and 6 are used for PCI (and are therefore supplied with VCCIO=3.0V), whereas the rest use the 3.3V-LVCMOS standard. Which configuration voltage standard should be chosen in that case, 3.0V or 3.3V? Or, in fact, all I/O banks containing configuration pins must use the same VCCIO level? I haven't been able to find any mention to such case in the documentation so far.
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