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Altera_Forum
Honored Contributor I
972 Views

How to compile cycloneIII_3c25_start_niosII_standard?

Hi, I have a Cyclone III Starter Board and I'm trying to compile the example Nios II project (cycloneIII_3c25_start_niosII_standard) that came with it. I have version 8.0 of the disk and I'm using Quartus 9.0. Here is what I'm doing: 

 

1. open the project 

2. regenerate the SOPC system 

3. add altmemddr_phy_ddr_timing.sdc to the project 

4. compile 

 

I get zillions of warnings, including critical ones. TimeQuest finds violations associated with the JTAG debugger clock altera_reserved_tck and tells me that I shouldn'd trust the results because assumptions are violated. There are many failing filters, includings ones generated by the cpu.sdc and the altmemddr_phy_ddr_timing.sdc. Those scripts are pretty complex so I'm thinking a novice does not have much chance of debugging them. What's the deal? Does anyone know how to compile this successfully? I need some sort of secure starting point to work with. 

 

Thanks!
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2 Replies
Altera_Forum
Honored Contributor I
67 Views

Here's what I did: 

1 - Copy the project to a working folder (just so you don't taint the original). Make sure there are no spaces in your path. 

2 - Open project. Quartus asks if you want to convert the database from 8.0 to 9.0 to which you must respond yes. 

3 - Open SoPC Builder (it changes all of the components from version 8.0 to 9.0) 

4 - Generate SoPC Builder system. Exit SoPC Builder and save the system when prompted. 

5 - Replace the top level SDC file with the one I've attached. 

6 - Compile the project. 

 

You'll still get some warnings from the Timing Analyzer (from the cpu.sdc script generated by SoPC builder). Also, Multi-corner timing analysis fails one hold path on the Fast model. I wouldn't worry about it though. 

 

Jake
Altera_Forum
Honored Contributor I
67 Views

Just to clarify, there are two NiosII/CycloneIII reference designs: 

 

Cyclone III Starter Kit (CIIISB):  

cycloneIII_3c25_start_niosII_standard 

NiosII Embedded Evaluation Kit, Cyclone III Edition (NEEK): 

cycloneIII_3c25_noisII_standard 

 

These two designs are quite different. The original post was about the CIIISB example, not the NEEK example (but the NEEK example runs on the CIIISB as well).  

 

The file posted by jakobjones is for the NEEK example. I tried following his instructions. I found that I had to include this line at the top of his .sdc file: 

 

create_clock -period 20.000 [get_ports {top_clkin_50}] 

 

With this small change the compilation under Quartus 9.0 went well. I saw the same behaviors that he reports, except that the only timing failures were associated with the JTAG clock.
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