How to connect fpga subsystems w/o using physical fpga pins

[BillM256]

Hello,

I’m designing a system using the DE10-Nano. I’m designing with the Quartus Block Editor and it’s logic primitives. The system consists of a number of subsystem BDF files with I/O buses, that I then convert to BSF, bring the BSFs into a BDF system schematic and connect the buses in that system schematic.

But I’m missing something fundamental about how to connect my BDF buses. I’ve been assigning input and output buses to primitive pins in Block Editor, and consequently the buses show up on my system schematic. However, today I fired up Pin Planner and discovered those pins have been automatically assigned to actual very limited and valuable FPGA pins, and many of them are using even more limited GPIO pins. Until seeing this, I’d assumed my pins were symbolic internal fabric connections, not actual FPGA pins.

So, I tried deleting some of my pins, but the bus they were connected to also disappears from the system schematic, and I can no longer connect my subsystems.

There must be a way around such a profound limitation. Any help greatly appreciated.

TIA!

Bill McDonald

[sstrell]

What you see in Pin Planner are the Fitter placements for the top-level I/O (they're green, right?).  If you don't make any manual pin assignments, the Fitter selects locations for the top-level I/O because if you compile the design and then program the device, hardware pins need to be selected.  Fitter pin assignments are not written to the project .qsf file unless you back annotate them.

If you don't want any connections to hardware pins (though I'm sure you will eventually; just make manual assignments in the Pin Planner), add Virtual Pin assignments in the Assignment Editor to the I/O in question.

[BillM256]

Hi Sstrell,

 As always, many thanks for your help. I’ve embedded answers to your questions in red. I think your Virtual Pins are the solution, but I’ll keep issue open a little longer in case someone can offer more.

My best,

Bill

What you see in Pin Planner are the Fitter placements for the top-level I/O (they're green, right?).  As I understand, they’re a variety of colors. I’ll provide an inventory if you want. If you don't make any manual pin assignments, the Fitter selects locations for the top-level I/O because if you compile the design and then program the device, hardware pins need to be selected.  Fitter pin assignments are not written to the project .qsf file unless you back annotate them.

If you don't want any connections to hardware pins (though I'm sure you will eventually; Yes! But there are way too few pins to connect all subsystems. just make manual assignments in the Pin Planner), add Virtual Pin assignments Looks like Virtual Pin assignments is what I need. I’ll research. in the Assignment Editor to the I/O in question.

[sstrell]

By green pins I mean pins that have assignments made to them (filled shapes), not the colors used to identify the functions of a pin or its I/O bank, etc.  When you manually make a pin assignment, the pin turns reddish-brown.  When you reserve a pin, it turns blue.

As far as lack of pins is concerned, you only connect top-level I/O, the signals that need to connect to the outside world, to actual pins.  I think the "pins" you are thinking of are the pin symbols in the schematic editor.  Those should only be used for the top-level signals that connect outside.  Other connections should be made with matching names on wires.

[BillM256]

Many thanks, your latest further clarifies things.

As before, my comments embedded in red.

By green pins I mean pins that have assignments made to them (filled shapes), not the colors used to identify the functions of a pin or its I/O bank, etc.  When you manually make a pin assignment, the pin turns reddish-brown.  When you reserve a pin, it turns blue. Thanks, very helpful. As to green fill, I’m not seeing it. I’ve attached a clip of my Pin Planner. Regardless, the list at bottom of Pin Planner shows 117 assignments, which apparently is max available as my design uses a lot more already.

As far as lack of pins is concerned, you only connect top-level I/O, the signals that need to connect to the outside world, to actual pins. This is what I understood from your previous; thanks for confirmation. Figuring out how to do this will solve my problem. I think the "pins" you are thinking of are the pin symbols in the schematic editor. Yes. Those should only be used for the top-level signals that connect outside.  Other connections should be made with matching names on wires. My concern has been that the buses, in and out, disappear from my System schematic when no pin is attached to the bus in the Subsystem schematic. This means I can’t connect Subsystems in the System schematic. I’ve attached a second clip that shows what I’ve been doing in the System schematic.

However, it sounds like connections will automatically be made for me if I name Subsystem outputs and inputs identically, e.g., A[1..2]. Right?

Thanks much again,

Bill

[sstrell · Accepted solution]

The All Pins list at the bottom of the Pin Planner shows all the top-level I/O signals as determined by Quartus that you can connect to I/O pins, not the signals that you've assigned to physical I/O pins of the device.  Again, if this is not what you expect for signals that should get connected outside the device and that most of these 117 are supposed to be internal signals, then it is probably because you have used the pin symbol in the schematic editor on all of these signals.  The reddish brown pins you see in the package view (the graphical view of the chip) are the manual pin assignments that you created.  You don't have to assign all the signals in the All Pins list to physical I/O pins, but again, they are showing up there because Quartus thinks they are top-level I/O that need pin location assignments.

As for the design schematic, you have to add names to the wires.  Right-click a bus, go to Properties, and add the name.  The end of the bus/wire will have an x on it and will connect to another bus/wire with the same name.

[BillM256]

Yes, your description on the pins is on-target. I'll get rid of them except where outside world I/O is actually needed.

I tried deleting a named Subsystem output pin and xferring its name to the Subsystem output bus it had been connected to. I think this is the approach you describe. But when I render the Subsystem BDF to BSF, and include it in the System schematic, the output bus still doesn't show up on the System schematic. 

Not sure what's going on with that, but you've guided me to a much more manageable problem, and I'll get to work on it tomorrow.

I know my questions are very basic, and I greatly appreciate your generous sharing of your expertise and time!

Bill

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