We have an Arria 10 FPGA with ARM processor. In Platform Designer one of the EMACs is routed to the FPGA logic. Currently we connected the emac_gtx_clk output of the hps to the emac_tx_clk_in and emac_rx_clk_in inputs of the hps.
The EMAC is shown as network interface at the ARM processor (which is running Linux). When sending raw Ethernet data to this network interface, we can see with signaltap that each byte is sent twice. Signaltap uses the same emac_gtx_clk clock which is set to 125 MHz in Platform Designer.
It looks like the clock is running at 250 MHz. Can I use the emac_gtx_clk as user clock in the FPGA logic, or do I have to generate my own 125 MHz clock and connect it to the emac_tx_clk_in and emac_rx_clk_in inputs of the hps?