This is in reference to Stratix 10 SoC FPGA Development Board (Document# 150-0321319 as shown on schematic page 1).
There are two QSFP connectors on board(J9 on page 16, J10 on page 17). There are few signals (e.g. ZQSFP0/1_MoselL, ZQSFP0/1_ResetL, ZQSFP0/1_LPmode) need to be driven at correct state. Schematic shows they are driven from U43 (MAX 10 part). Section 4.7.2 of User guide for this card mentions user needs to use i2c bus from Stratix 10 (BC25, BC26 pins) to access these signals.
I take it path is : Startix 10 (i2c master) -----i2c bus ----------- MAX 10 (i2c slave) ------ drives ZQSFP0/1_<signals>
I need to know i2c memory map inside MAX 10 device. I don’t see MAX10 in Table 46 . And then again I need i2c memory map for each register implemented in MAX 10 to drive those signals.
Pleaseprovide this information.