FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5230 Discussions

How to find FIFO ID in FPGA architecture

Altera_Forum
Honored Contributor II
827 Views

Hi, 

 

To write data to a FIFO on FPGA from host through PCIE in DMA mode, by using Terasic PCIE IP, I need to specify the 'memory FIFO ID', how can I find the corresponding ID of a certain FIFO on FPGA architecture? 

Similarly, if this time the data is written to a memory-mapped memory, how to find the MM-address of the memory? 

 

I understand in SOPC/Qsys a certain base address is allocated to each component in the system, then does that mean Terasic PCIE IP has to be used with SOPC/Qsys? (doesn't look so from their reference design), then how to find the ID and the MM-address? 

 

Thanks!
0 Kudos
0 Replies
Reply