How to fix "OutOfMemoryError: Java heap space" error

[MSteg2]

We are building using the Quartus 11.1sp1 version (yes that is old but we have no reason to upgrade at this time)

I found where I can remove “DEAD” codespace by adding this to my Compiler options:

           -fdata-sections -ffunction-sections

And also adding this to my LINK options:

--gc-section

For our Fast Fare this worked and my codespace is now smaller, but for our Fast Fare-e (which uses more RAM) I get the following ERROR.

On the “nios2-elf-g++” command to do the LINK:

OutOfMemoryError: Java heap space

make[3]: *** [farebox__fastfare-e__release.elf] Error 1

make[3]: *** Deleting file `farebox__fastfare-e__release.elf'

make[3]: Leaving directory `C:/altera/fastfare/software/app/farebox'

make[2]: *** [.gfi_elf] Error 2

make[2]: Leaving directory `C:/altera/fastfare/software/app/farebox'

make[1]: *** [.gfi_build] Error 2

make[1]: Leaving directory `C:/altera/fastfare/software/app/farebox'

make: *** [fastfare-e.release.gfi_build] Error 2

There is virtually no difference in these two builds and the code is 85% the same but there are bigger RAM buffers in Fast Fare-e due to a larger Display (so bigger Virtual GUI Buffers).

How do I fix this so I can remove DEAD CODE from the build??

For now I removed the options and I am building fine...

[MEIYAN_L_Intel]

Hi,

May i know the BSP setting?

By clicking as below:

-right click the bsp project

-click Nios

-click BSP editor

The steps mentioned as below:

May you try to screenshot the main screen and linker script screen of the window open?

Thanks.

[MSteg2]

Attached is my “Settings.bsp” that you edit with the BSP Editor (and the settings.tcl if you need that), please tell me EXACTLY what needs to change with a step-by-step process if needed I haven’t “messed” with my BSP settings for years! Matthew B. Steger | Sr. Software Engineer T +1.847.871.1177 | M +1.630.254.2243 Genfare | 800 Arthur Ave | Elk Grove Village IL 60007 Genfare.com<https://www.genfare.com/> | LinkedIn<https://www.linkedin.com/company/genfare> | Customer Care<https://www.genfare.com/customer-care/> The information contained in this electronic mail transmission is intended by SPX Corporation for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender’s address records can be corrected.

[MEIYAN_L_Intel]

Hi,

There is no attached file found here.

May you try to attached again?

Thanks

[MSteg2]

Here is a ZIP of the settings.bsp and settings.tcl, let me know if you need anything else...

[MSteg2]

It has been a few days, did you get the attachment and you are looking at it???

[MEIYAN_L_Intel]

Hi,

Yes, I am looking into it.

There are two workarounds that you may try:

1. Change some BSP settings via the BSP editor. ie reduced driver, optimization, small c library, clean exit.
2. Increase on-chip memory size 

Thanks

[MSteg2]

Increasing RAM Size on the boards is out-of-spec, we have 15,000 boards already in-service that new S/W updates.

As I stated, it has be "a while" since I tweaked any settings in the BSP.

Please list EXACTLY what you want me to change in the BSP (not loose terms) including FROM and TO values and I can try that!

[MSteg2]

Have you decided what EXACTLY (including WAS/NOW) in the BSP you want me to change?

[Ahmed_H_Intel1]

Hi,

It is not guaranteed that if you choose the small C library, the design will fit inside your memory. You can give it a try and then if it gives you the same error you must increase the On-Chip memory or use an external memory if your code is huge. I recommend you to start first increasing the memory size. BTW what is the memory size you are using right now?

[MSteg2]

The EPCS is 8M and we have no problem fitting in that (code only no RAM) even though GCC Build thinks it won't fit due to us putting a BOOT (small code and FPGA load) in 1MB of EPCS and a ZIPPED Application in remaining 7MB. GCC Build thinks APP won't fit (and without being ZIPPED it probably wouldn't).

RAM is 16MB Total which must fit the APP code (no FPGA since that is loaded by BOOT) and all RAM variables.

[Ahmed_H_Intel1]

I am confused, which memory you use to keep the code and which for execution?

Can you tell us what are the NIOS II vectors? reset vector and Exception vector.

Regards.

[MSteg2]

We have an 8MB EPCS Flash and 16MB RAM and he RESET vector points to EPCS (BOOT).

• Lower 1MB of this is FPGA and BOOT
• Upper 7MB of this is our (zipped) APP ... which is built with SAME FPGA as BOOT (but does not have another copy)

At Power Up:

• The FPGA is loaded by H/W from EPCS Flash
• The BOOT is copied into RAM and Vectored to in RAM by H/W
• BOOT sees APP image in EPCS is VALID and unzips it to RAM and jumps to it (BOOT is now DONE)
• APP image runs out of 16MB RAM (using FPGA loaded from BOOT)

[Ahmed_H_Intel1]

Hi,

So if you are booting from the EPCS you can use the following:

1- Use "small Hello wold template" which turns off all the unnecessary libraries

2- Use optimization -O2 in the project settings.

These two options will give you the smallest code size of your application. If you still facing the same error you can use the XIP "Execute In Place" to save more size of the RAM which won't copy the .text region of the code to RAM (If the EPCS can fit the design)

In case if the EPCS cannot fit the design (FPGA+Zipped app) you can try:

1. To configure the FPGA from another memory.
2. Upgrade the EPCS flash. Configure the FPGA and Boot NIOS from EPCS with XIP on RAM.
3. Upgrade the RAM and Configure the FPGA from EPCS and Run the NIOS on RAM.

Otherwise I apologize if the design still out of memory, I have no clue to shrink it more than this to fit into the RAM and EPCS. Please let me know how can I help you.

Regards,