How to force manually in ModelSim one dada bus with value like sin(x)

[Savino]

Hi, I am checking to force manually some data bus like: input[10..0] in MOdelSim like here(by console):

force input[0] 0 0, 10, 10, ...... - repeat 200

force input[1] 0 0, 10, 10, ...... - repeat 200

ecc

There is a way to do it in automatic? I means, there is a way to load some file prewrite and add to console in some how? Or mauve by using some verilog or VHLD script that running when i click the simulation start in modelSIM

[Kenny_Tan]

You will need to write a testbench for stimulus.

We don't usually offer the code in the forum, but here is some example you can try out:

module testbench; reg [10:0] input_signal; integer i; real pi = 3.14159; real sin_value; initial begin for (i = 0; i < 100; i = i + 1) begin sin_value = $sin(2 * pi * i / 100); // Generate sine wave input_signal = sin_value * ((1 << 10) - 1); // Scale to 11-bit range #10; // Wait 10 time units end end endmodule.

Also, please take a look https://www.youtube.com/watch?v=Dm7Ow4XI22g on how to setup the testbench.

[Kenny_Tan]

Is there any further question?

[Savino]

yes, I tried to work with real value and $sin function but when i try to make systesys the message the the function real and $sin are non supported. If u have some way to fix it will be great.

[Kenny_Tan · Accepted solution]

In that case, you may create a module for the sine function:

module sine_generator (

 input wire clk,

 input wire reset,

 output reg signed [10:0] sine_out

);

 reg [6:0] index; // 7-bit index for 128 samples

 reg signed [10:0] sine_lut [0:127]; // 128-point lookup table

 initial begin

  // Precompute sine values and load them into the LUT

  sine_lut[0]  = 0;

  sine_lut[1]  = 50;

  sine_lut[2]  = 100;

  sine_lut[3]  = 150;

  sine_lut[4]  = 200;

  sine_lut[5]  = 250;

  // ... (continue with the full sine wave values up to 127)

  sine_lut[127] = -50;

 end

 always @(posedge clk or posedge reset) begin

  if (reset) begin

   index <= 0;

   sine_out <= 0;

  end else begin

   sine_out <= sine_lut[index]; // Output the sine value

   index <= index + 1; // Increment index for next sample

  end

 end

endmodule

[Savino]

tks a lot for all support

[Kenny_Tan]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.