I want a dsp2812 to generate three PWM signals and a I/O singal and input them to the MAX II starter kit. and is there a neccessity to make a middle circuit between two kits? Also, I want to generate 30 PWM singals for a multilevel MOSFET inverter using MAX II starter kit by the inputs from the dsp2812 kit. Is that possible? How to connect a DSP2812 starter kit and a MAX II starter kit? I think a synchronous frequency singal is important for the cooperation of two start kits. How to generate the synchronous using the dap2812 kit? Any suggestion will be better. Look forward to you reply.:o Thanks
as you are referring to a particular eval kit, itt would be appropriate to tell the exact type or better provide a link to the documentation. To design the link between both boards, you should know about the required data throughput.A common clock can simplify the interface.
Thanks, FvM. i want to use the two kits given the link as dsp2812 (TMS320F2812 eZdsp Start Kit (DSK) http://focus.ti.com/docs/toolsw/folders/print/tmdsezd2812.html ) and Max II starter kit (http://www.gfec.com.tw/pro_flypage.php?language_page=english&class1_serial=1&class2_serial=&class3_serial=&p_serial=11).Its my first time to design a inverter system for a motor drive. I am a starter and not familar with FPGA eval kit and just select a more cheaper one with download cabe from the Altera homepage. I cannot spend more money on this kit and not very sure it can work on my experiment. i just want a dsp2812 eval kit to generate 3 basic PWM singals, 1 i/o singal and a common clock, which are sent to a FPGA eval kit to obtain 30 PWM singals for a designed multilevel inverter. Thus, the question are 1). how to generate a common colck using a given dsp eval kit? using I/o or other outputs? how to generate it in the dsp28112? 2). should i make a middle ciucuit board for the cooperation of two eval kit? I think the requrement of two kits have the same voltage of 3.3V. Maybe we can directly connect them together and not need other middle circuit. is that right? 3). The FPGA eval kit may be not very appropriate. This is a very old version. the eval kit of Altera or Xilinx, etc. company may be a better choise for me. I just want a simple, cheap and good FPGA eval kit for my experiment. would you give me a suggestion for a better eval kit to my experiment? Any suggestion is more better. my email is given at the bottom. None can give me some suggestions except my research and question by the internet. i need more good suggestion. Thanks for you reply again. If possible, after finished this experiment, i can share more detailed information of my experiment with you to thank for you help. looking forward to your reply. Allin (email@example.com)
You need to take a good look at the documentation and see what each kit has and how you can make use of it.1) Each kit has it's own oscillator. From a quick look at the specs, the dsp2812 kit has a 150 MHz clock oscillator and the MAX II kit has a 16 MHz clock oscillator. 2) The MAX II can handle 150 MHz but if you want to operate the interface between the MAX and the dsp at 150 MHz, you'll need a well designed PCB. Operating at 16 MHz can be done with just wires connecting the two boards. 3) First, figure out what the FPGA needs to do. Then, you can implement it and simulate it and see what FPGA you need. You need to take a look at the dsp2812 kit, the DSP chip in it and figure out what kind of interface it presents on the I/O expansion pins. Then figure out what you need to have the dsp and the FPGA do.
I'm not familiar with the TI DSP details, particularly I'm unable to locate a dsezd2812 schematic to understand the available IO interconnect option. Thus I don't know, if you can easily output a derived clock.On the MAXII side, there should be no problem to operate the design from an external supplied clock instead of the on-board clock oscillator. This can save the effort for synchronizing the input signals from DSP. Because MAXII has no clock managment options, the clock frequency has to be suitable to operate the design. MAXII logic resources are limited, so the "division of work" between both digital chips should be well considered. Are you already clear about the algorithm to generate the multi-level PWM signals?
Thanks, rbuqalho and FvMIn the DSP2812, There is a general-purpose clock source output of xclkout, which is either the same frequency, 1/2 the frequency, or 1/4 the frequency of SYSCLKOUT (150MHz). I can use it (150MHz or 75MHz or 37.5MHz) as a common clock for two kits. As rbuqalho said, a middle circuit board have to be achieved for the interface between two kits, which is big problem for me. I guess it maybe concern of frequency transformation to all my required output signals. I cannot figure it out, which is outside of my ability. Could you give me a detailed explanation for it? I plan to generate three 10KHz PWM signals by DSP2812, and a I/o signal and a 150MHz common clock by the DSP2812. I know the algorithm to generate the multi-level PWM signals, which is about some simple logic operations. A easy, fast and cheap FPGA is good for my expectation. Until now, I just find the kit of MAX II starter kit. Maybe it has little good resources to programme. Is there a good alternate kit for my experiment? Besides, I originally plan to realize all the algorithm by only one FPGA kit. However, the designed algorithm contain more mathmatical function, which is suitable to be achieved by a DSP chip. Thus, If i realize that in one FPGA kit, is there a good FPGA eval kit for my thinking? Any suggestion will be better. Thanks. Looking forward to your reply.
I expect, that a simple cabel should be sufficient to connect both boards. 75 MHz will be probably good as a MAX II clock.Without an idea about the complexity of multilevel algorithm, I can't determine if a MAX II can handle it. Code the algorithm in VHDL or Verilog and see how much resources it consumes. P.S.: For medium resource requirements a Terasic DE0 (Cyclone III, 16k LEs) or DE0-Nano (Cyclone IV, 22k LEs) should be suitable. Both have GPIO headers to connect 3.3V LVCMOS signals.