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How to infer a FIFO using registers/ALM and not block RAM ?

VRb
Novice
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The synchronous logic being used for FIFO is infering Block RAM.  I have tried ramstyle as auto,MLAB,LCs but it still does infer block RAM.  How can I infer the FIFO using registers. It is a 512x5 register but Quartus is inferring 13 block rams on one of Stratix 10 device. I want this FIFO to use an ALM. (13 Block RAM for 2560 bits of memory is too much). Read and write can happen in same clock(this has a show ahead feature meaning read data is there at the output before reading).

The design uses other 82 block RAM's but that seems reasonable for the depth instantiated. 

 

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RichardTanSY_Intel
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You can set the FIFO parameter setting use_eab to OFF. You may checkout the FIFO UG below.

https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/fifo-parameter-settings.html


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VRb
Novice
653 Views

How can it be done using the ramstyle attribute ? 

 I tried using MLAB but still it inferred Block RAM. I was able to understand this was due to the style of coding. Can I still force it to use ALM's ?

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RichardTanSY_Intel
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Do you able to get the desired behavior?


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VRb
Novice
610 Views

Using the attribute still inferred memory with M20K. I alternatively instantiated a RAM (from intel IP) and then used the instantiation as memory to build my FIFO. I am able to generate a ALM based memory in this case. 

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RichardTanSY_Intel
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That works as well. I trust that you will proceed with the alternate solution that you have found.


With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos and select the best solution. 


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