- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I use an Cyclon V SoC FPGA (on an DE10-NANO). I would like the to use the integrated DMA Controller from HPS (no IP Core on Platform Designer) to write Data from my own buffer to the HPS2FPGA . Have anybody an Example how to inizialise the DMA Controller? Thanks!
- Tags:
- Cyclone® V FPGAs
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
I couldnt find an example supported by Intel PSG to use HPS DMA instead of FPGA DMA. the reason behind that is, the FPGA DMA is much faster compared to HPS DMA.
You can refer to this example:
https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/DMA_PL330_LKM
You might find some interesting information.
Thank you
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thank you for your first answer. But I would like to copy data from Buffer on HPS to another/other buffer on HPS and the HPS has an DMA Controller - why should I use the FPGA DMA (speed is not so interesting)?
I have bind in the libs alt_dma.h and alt_dma_common into my main.c file. So every time when I uses fuktion from that libs (fokused alt_dma.h) I get linker error. Why doesn't work?
Thanks for your answer.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello sir,
Data transfer is needed usually between FPGA and HPS, this is what we call it DataMover Application. FPGA mSGDMA will be more advanced and has more features that can support the data transfer between HPS and FPGA. And this is the application that we have..
In your case, you are looking for a data move application from HPS to HPS through buffers, where the FPGA DMA is not helpful. Unfortunately, we dont have such application.
You might refer to the link I sent earlier to help you find a closer application to fix your design issue. Please note in this design it considers the FPGA as destination, in your case, you need to change it to another destination (SDRAM or Buffer).
Thank you.
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page