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Hi,
I use terasic DE3 with an external DDR2. The DDR2 demo given by terasic is running good but the DDR2 data is generated inside the NIOS. How should I load data from FPGA to the NIOS processor? Thanks!Link Copied
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In SOPC, use DMA or SGDMA.
In Nios IDE, use IOWR and IORD.- Mark as New
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Hi sean,
Thanks for your reply. But the IOWR/IORD can run at most at around 20MHz, right? That means the highest data rate I can get is 20*64=1280Mbps, which is a huge decrease in performance. Is there any solution for that?
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