I am using DEVICE 1SX280HU2F50E1VG. Enabling RS-FEC in the 100GE IP core defining widow places this device in the data path. The problem I have is I can't make the RS-FEC block work. No packets are coming back in a loop back mode. The packets are present and all statistics counter look good when I remove the RS-FEC from the design. Is there something I am missing regarding this IP?
Thank you, Zoran
thanks for the quick response!
Q) May I know which Quartus version that you are using ?:
A) I have used 18.1 and had this proble. Right now I use Q 19.1.0 Build 240 and still have the same problem.
Q) Stratix 10 FPGA contains few Ethernet IP. Are you referring to "low latency 100G Ethernet Intel FPGA IP" or some other Ethernet IP ?:
A) I use low latency 100G Ethernet Intel FPGA IP.
Q) Do you encounter the issue in simulation or actual hardware testing ?
A) I see the problem while testing on hardware, in house developed board.
Q) Can you elaborate further on your loopback testing ?
A) I enable loopback testing by writing 0xF to the appropriate address, 0x300313). The loopback works well with no RSFEC present.
I monitor diagnostics counters for the info regarding the TX and RX frames.
Also I have all relevant signal on the internal logic analyzer so I could see by naked eye what is going on. And what I see there are TX packets but no RX packet.
When with no RSFEC the data packets are visible in both direction.