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Altera_Forum
Honored Contributor I
795 Views

How to program an I/O as a open drain on MAXII Micro Kit by using Quartus II?

Hi, 

 

Are there anyone knows how to program an I/O as a open drain on MAXII 

Micro Kit by using Quartus II? I saw the MAXII device handbook. The MAXII 

supports a function of open drain for the I/O. It can also support an internal 

I/O clamp diode in I/O bank3. I, however, couldn't find any options on the 

pin assignment of the Quartus II. I don't know what is wrong. Are there 

anyone could tell me why? The Micro kit is a development kit from Terasic. 

It has a CPLD EPM2210F324C3N. If you need any other information, tell me 

please. Thank you! 

 

 

Peter Chang:)
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3 Replies
Altera_Forum
Honored Contributor I
85 Views

I've seen a post which uses a command as below in QSF. 

 

set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to xxxxx 

 

I've tried. I, however, couldn't find any difference on the Quartus II. 

How can I know if the pins have been programmed as a open drain 

output? Thanks. 

 

Peter Chang
Altera_Forum
Honored Contributor I
85 Views

Most FPGA users define open drain function in HDL by assigning '0' respectively 'Z' output state, because it's a portable method working with any tool and CPLD vendor.

Altera_Forum
Honored Contributor I
85 Views

Hi FvM, 

 

Thank you! It must be the easiest. 

 

Peter :)  

 

Most FPGA users define open drain function in HDL by assigning '0' respectively 'Z' output state, because it's a portable method working with any tool and CPLD vendor. 

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