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How to recompile verilog code with slight change in reg value using previous fitter(Place & route)

jkhoo
Employee
220 Views

I have a working compilation with the Fitter (Place & route) generated by Quartus 18.1. When i change a value in a 32bits register

from 

assign PROD_VERSION = 32'h0008_0008;

to

assign PROD_VERSION = 32'h0008_0009;

I saw the Fitter replace and reroute my verilog causing the compilation behavior change.

 

Is there a way to maintain the Place & Route on a working compilation while in the same time change the version id? instead of letting Quartus replace and reroute the logic.

 

Or is there a way to extract the Place & Route of fitter from a working compilation and reuse in next compilation while changing the register value for differentiating the version?

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7 Replies
RichardTanSY_Intel
209 Views

Quartus is not able to rerun full compilation a design without running fitter.

https://www.intel.com/content/www/us/en/support/programmable/articles/000084189.html


You can design partition and preserve the fitter(final) database, a portion of the design. Instead of the whole design undergo P&R.

https://www.intel.com/content/www/us/en/docs/programmable/683247/19-4/design-partitioning.html


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.



jkhoo
Employee
192 Views

HI Richard,

Thanks for the guidance, will try out your suggestion.

from JJ

RichardTanSY_Intel
153 Views

May I know do you need further help in regards to this case?


Best Regards,

Richard Tan


RichardTanSY_Intel
139 Views

Any update on this?


Best Regards,

Richard Tan


jkhoo
Employee
136 Views

I try your suggestion to logic lock and design partition on the intended module/instance of the verilog code on the working compilation. Once i box them, i recompile with a purpose to export out the qxp file. But i notice once i box it and recompile, the cells of the module in the floor plan is no longer matching the initial place and route. Seem that by boxing the intended module without changing the verilog code will cause the fitter to place and route differently in the floor plan. 

Is this a normal behaviour of the fitter that logic lock and creating the design partition will cause the place and route to change?

RichardTanSY_Intel
128 Views

Are you referring to the first compile after the design partition? If so, then yes.

The subsequent recompile should remain/no change.

 

You may checkout the KDB on what may cause the compilation results changes.

https://www.intel.com/content/www/us/en/support/programmable/articles/000084189.html

Also, it mentions that "the first compilation after turning on a preservation option may have different results than the previous compilation for portions of the design that are not preserved. Subsequent compilations with no changes will be identical."

 

Hope that clarify.

 

Best Regards,

Richard Tan

 

RichardTanSY_Intel
53 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. I now transition this thread to community support. Please login to https://supporttickets.intel.com, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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