I have Arria10 SoC Dev Kit. I want to use it's UART modules in my FPGA logic but all 2 of them connected the HPS side. They connected HPS shared I/O pins. So I can be route them to FPGA. I used platform designer, created a HPS IP and route the UARTs to the FPGA then export the pins. But when I try to work with UARTs they seem they are not control of FPGA. They print HPS debug stuff or nothing. I cannot receive or transmit anything from them. Should I change the HPS side? Like linux device tree or someting? Or the platform designer arrangement suffice this work? If so what do I do wrong?
HPS peripherals are accessed by FPGA logic through the F2H bridge, which it looks like you've enabled but not connected to anything (f2h_axi_slave). An address map is set up so the FPGA logic can access the HPS peripherals through normal memory-mapped addressing.
You make connections in Platform Designer to IP you add to the system there or export the interface and connect to HDL code you write through port mapping. You should learn more about how to use Platform Designer to help understand what you need to do. You can start here:
I came across this link below, hopefully it will help to your question regarding axi buses.