I'm trying to set the first bit in a logic vector to 1 so that the number is signed as a negative
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Hi Rory,
Yes, you can change a single bit in a vector without impacting other bits.
Example:
Data : in STD_LOGIC_VECTOR (15 downto 0);
x: out STD_LOGIC_VECTOR (15 downto 0);
.......
signal signBit : std_logic:='1';
......
signal sig : std_logic_vector(31 downto 0);
.......
sig(31)<=data(15);
signBit <= Data(15);
x(15)<='1';
Regards
Anand
thank you so much that's really helped.😁
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