FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5151 Discussions

How to set the most significant bit in an STD_LOGIC_VECTOR(data_width downto 0) to 1 without changing the other bits

rgodw
Beginner
393 Views

I'm trying to set the first bit in a logic vector to 1 so that the number is signed as a negative

0 Kudos
2 Replies
AnandRaj_S_Intel
Employee
149 Views

Hi Rory,

 

Yes, you can change a single bit in a vector without impacting other bits.

Example:

Data : in STD_LOGIC_VECTOR (15 downto 0);

x: out STD_LOGIC_VECTOR (15 downto 0);

.......

signal signBit : std_logic:='1';

......

signal sig : std_logic_vector(31 downto 0);

.......

sig(31)<=data(15);

signBit <= Data(15);

x(15)<='1';

 

Regards

Anand

 

rgodw
Beginner
149 Views

thank you so much that's really helped.😁

Reply