Hello,I have the Arria V GX 5AGXFB3H4F40C5. I program it with Quartus II 13.1 in windows 8.1 the questions are at the end of this message. I'm trying to set up one transceiver as transmitter TX with only one channel which works at 1GHz or 800Mhz, frecuency must be selected by the user pressing the push buttons. That's why I add one Reconfiguration Controller in the block design file for the Native PHY Transceiver IP Core, also I add the Reset Controller too. So I have got 4 blocks in the desing file: The Reconfiguration Controller, the Reset Controller, the Tranceiver IP Core and my own logic block (written by me in VHDL) My logic block receives the pressed signal from the push button and then sends the needed data to the reconfiguration controller for switching the frecuency of the Transceiver. i have read the transceiver's section in the manual, so i think i know how to use the avalon memmory mapped system for reconfiguring the pll reconfiguration registers.
I have used the Derive PLL clocks function and the Derive Clock Uncertaintly. I have saved it in de sdc file, I have added the sdc file to the project and recompiled it again. the questions are:
Which is the pin number I must assign to my signal tx_serial_data in the assignment editor? I searched it in the manual and I didn't find it. SMAs ports don't send any signal. Now I have assigned the PIN_J3 but It's not working. Why do I have this warnings? Specialy the last one Warning (332043): Overwriting existing clock: alt_cal_av_edge_detect_clk Warning (332174): Ignored filter at Trans5.out.sdc(94): sv_reconfig_pma_testbus_clk_0 could not be matched with a clock Warning (332035): No clocks found on or feeding the specified source node: inst1|controlador_inst|basic|a5|reg_init|clk Warning (332060): Node: transmisor:inst|altera_xcvr_native_av:transmisor_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts.gen_bonded_group_native.av_xcvr_native_inst|av_xcvr_avmm:inst_av_xcvr_avmm|avmm_interface_insts.av_hssi_avmm_interface_inst~BURIED_ASYNC_DATA_OUT was determined to be a clock but was found without an associated clock assignment. Can anyone give me a link to a tutorial for setting up this trasnceiver in this FPGA? Can I send signals at less frecuency than 800mhz with the Native Transceiver PHY IP Core?
Are you using a SMA loopback cable on the board? If so where do you connect it? Or are you using a HSMC loopback connector?It could also be smart to simulate your RTL code first so you know that it's functionally correct. Writing a testbench would be pretty simple since you just have to provide the clocks, refclock, reset, and the loopback. However, it can be some amount of work to set up all the IP files which goes into your simulator.
Thanks for answering!I'm using SMA connectors. I have disabled the loopback option cause I look the signal output in an oscilloscope. I connect the J5 with the probe of my oscilloscope with an SMA wire. Now I know that the PIN_G32 and PIN_G31 are the pin numbers for my reference board SMA connector J5, positive and negative respectively. Also I have done the same project without reconfiguration controller, working only at 1GHz and using a custom PHY Transceiver instead of Native. And now it is working, it is sending data by J5 board reference connector. Furthermore I have not warnings. May be important to say that my logic block, written by me in VHDL, is in this design. So I know is ok. I will do the receiver part now, I won't try to use the reconfiguration controller any more. can any one tell me the pin numbers for my sma rx board reference connector j3?
I wasn't thinking of internal loopback. Only if you were using SMA (which you seem to be using) or HSMC. Didn't you get a schematic or reference manual with your board?
I use SMA connectors but I didn't find the association pin number for my SMA RX board reference connector J3 in the Arria V reference manual. Neither for the J5
You will not find that in the Arria V reference manual, but you should find it in the schematics and/or reference manual for the development kit. Do you have that?
If you go to the kit's page (http://www.altera.com/products/devkits/altera/kit-arria-v-starter.html), you can download the "kit installation" archive (if you don't have it on DVD) and from there you can find the board schematics. Then it should be easy to find what FPGA pin J3 is connected to.It's a shame they forgot to put that in the user manual, but from prior experience with Altera kits, it's a lot safer to rely on the schematic than the documentation to find out which FPGA pins to use.
Thank you, I found the schematics file. It is called A5GX_STARTER_C.pdfThe pin_number association for SMA receivers are H34 and H33, positive and negative respectively. So board reference J2, J3, J4 and J5 are associated to pin numbers H34, H33, G32 and G31 respectively. But now I cannot understand why it's sending a clock signal the rx_clkout from my custom transceiver if I don't connect any input signal to the RX channel. does custom transceiver send a fake clock signal by rx_clkout pin even if it has not any input signal by rx_serial_data pin?