FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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How to solve this Fitter error?

CHung
Novice
736 Views

Hi,

As attached file, Quartus shows "Fitter require X LABs for clock region in ..., but only Y LABs available ...".

What does this message mean?

Do you have any suggestion for solving this problem?

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5 Replies
KhaiChein_Y_Intel
537 Views

Hi,

 

This error is issued when the legal clustering cannot be found in a region. It could be a clock region, a Logic Lock region, or an intersection of both.

 

In this case, please increase the size of any Logic Lock region or the clock region in the corresponding locations.

 

Thanks.

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CHung
Novice
537 Views
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KhaiChein_Y_Intel
537 Views

Hi,

 

May I know if you have any updates?

 

Thanks.

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CHung
Novice
537 Views
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Zhilang_X_Intel
Employee
537 Views

Hi KhaiY,

 

Could you help share about how to increase the size of any Logic Lock region or the clock region in the corresponding locations

 

Thanks!

Liam

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