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MLOPE14
Beginner
287 Views

How to start DMA from FPGA-memory to PCIe Domain, once the FPGA has the data ready? How to set the FPGA as the DMA Master?

Using Cyclone 10 GX FPGA Dev Kit. 

Reference: Intel® Arria® 10 Avalon-MM DMA Interface for PCIe.

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3 Replies
Nathan_R_Intel
Employee
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Hie, My apologies for the delayed first response, as I missed your question. There were few PCIe DMA cases assigned to me, that I missed this one. For Cyclone 10 is using PCIe with DMA, our recommendation is to use the Intel Arria10/Cyclone 10 Avalon-MM DMA for PCIe Example Design. Once the FPGA is configured, the Physical Layer will link up and followed up by enumeration. The Example Design uses a On-Chip Memory IP-core which stores the DMA data. For the FPGA, you will need to use the Descriptor Controller to manage the Read and Write DMA. The steps to generate this Example Design and its usage is covered in the following user guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm_dma.pdf Please let me know if you understand my response above and you have further questions. Regards, Nathan
MLOPE14
Beginner
81 Views

Hi Nathan,

 

Thanks for the response. I understand your suggestions. The link you provide is newer than the one I have been using. I will study it, concentrating in the Descriptor Controller.

So far I am on track with your suggestions. I am using the Arria10/Cyclone 10 Avalon-MM DMA for PCIe Example Design; it does read/write the application layer registers; and responds to Legacy Interrupts; it will use On-Chip Memory for DMA transactions. Descriptor Controller is next.

 

Can you briefly describe the difference between using the Descriptor Controller internally instantiated or when it is not?

 

Regards,

Martin Lopez

Nathan_R_Intel
Employee
81 Views

Hie Martin Lopez, Using the Internal DMA Descriptor allows user to manage read and write DMA operations. The DMA Descriptor Controller includes read and write data movers to perform local memory reads and writes. It supports up to 128 descriptors for read and write DMAs. Host software programs the DMA Descriptor Controller internal registers with the location and size of the descriptor table residing in the PCI Express main memory. The descriptor control logic directs the DMA read logic to copy the entire table to its local FIFOs. Using the External DMA Descriptor Controller provides more flexibility. You can either modify or replace it to meet your system requirements.You may need to modify the DMA Descriptor Controller for the following reasons: • To implement multi-channel operation • To implement the descriptors as a linked list or to implement a custom DMA programming model • To store descriptors in a local memory, instead of system (host-side) memory To interface to the DMA logic included in this variant, the custom DMA descriptor controller must implement the following functions: • It must communicate with the Write Mover and Read Mover to copy the descriptor table to local memory. • The Write Mover and Read Mover must execute the descriptors stored in local memory. • The DMA Avalon-MM write (WrDCM_Master) and read (RdDCM_Master) masters must be able to update status to the TX slave (TXS). Regards, Nathan
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