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Beginner
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How to tell quartus for multiple clock

I have part of my disign for Stratix V, that works on rx_std_clkout and tx_std_clkout from Transceiver Native PHY IP core, and dynamically change speed via Transceiver Reconfigurator IP core. I use word aligner, 8b/10b codec, byte ordering. 40 bit bus. But I think, that quartus not compile my design well, and how can I tell, that I want to work on different speed?

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Moderator
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Re:How to tell quartus for multiple clock

Hi,


Just to ensure we are on the same page, would you mind to further elaborate on the "quartus not compile design well" observation? Just wonder if you are referring to timing constraining your design which will be working on different speed?


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



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Beginner
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Re: Re:How to tell quartus for multiple clock

No, I mean, that, at start speed of Native Phy speed 2,5Gb and rx and tx clkout has freq 62,5 Mhz, than I dynamically reconfigure to 5Gb and 10Gb, so my tx and rx clkout has 125 and 250 Mhz. But I think, Quartus compile good only for 62,5 Mhz, and when I change speed, it works not good as I expected. So question is, how to tell Quartus in my project, that my modules have to work good at every clk, 62,5 , 125, 250 Mhz.

P.S. I think, if I set at beginning speed 10Gb and then downgrade to 2,5Gb, its not good idea too.
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Moderator
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Re:How to tell quartus for multiple clock

Hi,


Thanks for your update. Yes, you are right, when you perform dynamic reconfiguration, the tx/rx_clkout frequency will change according to your new XCVR data rate.


Would you mind to further elaborate on what is referred by "it works not good as I expected"? For example, do you observe your core logic behave incorrectly?


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



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