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How to use FPGA side SDRAM on Cyclone V SoC

​Hi, There are two SDRAM (each of 1GB) on cyclone V SoC (Arrow Sockit Board (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=816)) (5CSXFC6D6F31C8ES), one for HPS and one on the FPGA side. I wana know how to use SDRAM on FPGA side. Is it possible to write to this SDRAM on fpga side from HPS? I made following system but when ever I try to execute my C program, it Stucks. Any help will be appreciated.

Capturef.JPG

 

 

Here is my C code to HPS.

#include <stdio.h> #include <unistd.h> #include <stdlib.h> #include <stdint.h> #include <fcntl.h> #include <sys/mman.h> #include <sys/types.h> #include <sys/stat.h> #include "C:\altera\15.1\embedded\ip\altera\hps\altera_hps\hwlib\include\hwlib.h" #include "C:\altera\15.1\embedded\ip\altera\hps\altera_hps\hwlib\include\soc_cv_av\socal\socal.h" #include "C:\altera\15.1\embedded\ip\altera\hps\altera_hps\hwlib\include\soc_cv_av\socal\hps.h" #include "C:\altera\15.1\embedded\ip\altera\hps\altera_hps\hwlib\include\soc_cv_av\socal\alt_gpio.h" #include "D:\TestDesigns\SoCKit_DDR3_Nios_Test\hps_0.h" #define REG_BASE 0xC0000000 /*AXI H2F SLAVE Address*/ #define REG_SPAN 0x00200000 volatile unsigned char *reg_addr; /*this is the pointer that reads from the register*/ void* virtual_base; /*pointer to open device memory file*/ int data[8]; int i; int main () { int fd = EXIT_FAILURE; fd=open("/dev/mem",(O_RDWR|O_SYNC)); if (fd < 0) { perror("open"); exit(EXIT_FAILURE); } printf("fd is ok\n"); virtual_base=mmap(NULL,REG_SPAN,(PROT_READ|PROT_WRITE),MAP_SHARED,fd,REG_BASE); printf("virtual base pointer to open device memory file is ok\n"); reg_addr = (unsigned char *) (virtual_base+MEM_IF_DDR3_EMIF_0_BASE); /*accessing base address of register*/ for(i=0;i<8;i++) { data[i]=i+1; *reg_addr=data[i]; reg_addr=reg_addr+1; printf("//////////////////////////////\n"); } for(i=0;i<8;i++) { printf("the output value from the SDRAM is %d\n",*reg_addr); reg_addr=reg_addr-1; printf("//////////////////////////////\n"); } return 0; }

 

 

 

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Hi matif,

 

Thank you for joining this Intel Community.

 

I suggest you to use Golden Hardware Reference Design (GHRD) as a hardware project starting point and see how everything is connected through Qsys.

 

To do so, you need to install SoC EDS with Quartus, then you will get an example design in <SoC EDS installation directory> \examples\hardware \cv_soc_devkit_ghrd

( for example :C:\altera\15.1\embedded\examples\hardware\cv_soc_devkit_ghrd )

 

Here is the link to the project: https://rocketboards.org/foswiki/Documentation/AVCVGSRD151

 

You may refer to this design guideline for more details: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-cv-av-soc-ddg.pdf

 

Hope this helps. Let me know if you have any concern.

 

Thanks

 

Regards,

NAli1

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Hello matif,

 

Also, here is some additional debug suggestion from me 😊

 

As I can see that everything looks perfect in your qsys connection attached. So, perhaps you can try to run the calibration and see if it pass/fail.

Next, I will suggest you signaltap (stp) the avalon-MM interface and check which signal is not behave unexpected causing the code to stuck.

 

Thanks

 

Regards,

NAli1

 

 

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Hi,

thank you so much for your reply. Can you give me some example link on how to do calibration for pass/fail?

 

And all the GSRD or GHRD designs I have seen so far just implement design of either SRAM or SDRAM on HPS but what I need is an example that show me how to use SDRAM particularly only on FPGA side.

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Hi matif,

 

To perform memory simulation, you can refer to Chapter 8. Simulating Memory IP on page 468 of this handbook which have all the step by step instruction in order to run calibration. --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan...

 

The following table lists signals produced by the calibration process to show on the calibration pass/fail result.

calibrationsignal.PNG

Here is some additional info that I think is useful which to share with you. 😊 If you're interested to know more details on the UniPHY IP calibration stages, you may refer to Chapter 1.17. UniPHY Calibration Stages (page 55) of this handbook --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.p...

 

 

Thanks

 

Regards,

NAli1

 

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Novice
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​Hi,

thank you  for the support. I did the calibration checks on my board and calibration tests are all fine. Now I wana do simualtion but simulation is not fine. I followed the steps in the documents as you provided. Here is a screen shot. Any ideas on what I can do.Capture.JPG

 

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Hi matif,

 

Seems like the simulation is still running. It require some times to be completed. If you are running with "Full Calibration" mode, the estimated synthesis time taken is much longer.

simulation time.PNG

Anyway, this is just the estimated time. The real simulation time for your design may vary depending on the memory interface specifications, simulator, or the system you are using. And it is recommended to use correct Synthesis tool (ex: ModelSim, Synopsys..etc) that is compatible with your Quartus version.

 

Also try using other simulation tools for better simulation times (For eg : synopsys VCS simulation run time is much faster as compared to other tools) as different synthesis tools give different results.

 

Thanks

 

Regards,

NAli1

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Oh.. Okey. thanks a lot for this information. I ll wait for the simulation to complete and let you know then.

Thanks for your support.

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Novice
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Hi, thanks a lot. Ran the simulation for one day and got the reuslts.

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Hi matif,

 

You are more than welcome 😊 Glad to know you have got the results.

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