I assume the DE10 Lite board state can't be assumed after power up and also it should be a better practice to use reset signal - also for the simulator.
Can someone provide me a design example with pin assignment with reset signal?
If you are just looking for FPGA pin assignment setting for DE10 lite board then you can refer to below link to get the reference "qsf" file
However, feel free to checkout DE10 board user manual and reference design in below link
PDF is the user manual doc while reference design info is mentioned in doc chapter 5 "modifying the DE10-Lite Computer"
I didn't find any reference to the reset behavioral and spec: Is there an on-board reset signal on the DE10 Lite? Does it go active after power up? for how long?
There is no reference design or guidelines, except for F16 pin which goes to the Arduino header. I am not sure if this is an input to the FPGA from the board, or output from the FPGA to the Arduino header.
The QSF file refers only to Arduino header reset, mentioning the F16 pin.
Can I assume that by design the FPGA signals are all zero?? In "classic" chip design this is a wrong assumption.
You can find all the board component detail of DE10 board in the user manual doc
For instance, typically we use on board push button or slide switch to control the reset signal to FPGA design. (refer to user manual chapter 3.3 for the FPGA pin location)
Then for your other questions - FPGA default power on GPIO pin signal stage will be tri-state with weak up. It's not zero.
Yes - i noticed the switches, and I know how to use them to generate input, as they are general purpose.
Yet I wonder: is that a dedicated reset signal on board?
I would like to use this signal as an input to my verilog code, so whenever the board goes through reset, the FPGA content will be reset too. (same way it would have been done if the verilog file would go to chip design - reset is a must).
Using external switch will not be aligned in such case.
I understand that GPIO goes to 3-state. makes sense. However, my question was about the internal FPGA's FF's. I would like them to be set a to certain values when reset occurs.
I understand your intention now but sorry, the feature request is not available on DE10 board.
DE10 lite board is just simple demo board meant to showcase FPGA feature and capability. The board is not designed to fit into real system design application.
For your enquiry on FPGA FF,
- If you are designing your own FIFO logic, then you should be able to configure the default state yourself
- Else if you are using Intel FPGA FIFO IP core then it will has its own control mechanism where you can read more about it in below link
You can simply google for Intel FPGA IP core user guide to find out more about its usage.
You shouldn't need to worry about the default value of register.
Just like what you said, good design practice is to always reset the FPGA design before user start the functional operation. By performing reset operation, then you can force your design to known default state value that you want.
Agree to that.
So how do I perform a reset operation?
One way is manual: connect a switch and press it.
Is there an automated way to provide a RESET signal as input to the FPGA?
So once the image of the design is loaded, I will use it in my logic to bring the FFs to a preset values?