How was fpga.dts on de10-standard GHRD generated?

[Altera_Forum]

Hi, 

 I sent a support question to Terasic but while I'm waiting for the response, I was wondering if anyone on this forum knew how the fpga.dts file in the Demonstration/SoC_FPGA/DE10_Standard_GHRD example was created.  Thanks, Raul

[Altera_Forum]

Hi, 

 Steps to generate device tree (dts/dtb)  Dts = can view  Dtb = binary, cannot view. 1. Compile Quartus 2. Get handoff folder / handoff_isw 3. Get <projectname>.sopcinfo 4. Use sopc2dts tool to convert # sopc2dts   Xml file, from customer board designer. 5. sopc2dts --input soc_system.sopcinfo --output socfpga_new.dtb --type dtb --board soc_system_board_info.xml --board hps_common_board_info.xml --bridge-removal all –clocks  For more information check the link http://www.alterawiki.com/wiki/sopc2dts#intro https://rocketboards.org/foswiki/documentation/gsrddevicetreegenerator  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

Hi Anand, 

 Thanks for the reply. Step 5 will generate a socfpga_new.dtb file where dtb = device tree blob.  However, when I look at the DE10-Standard_User_Manual.pdf, Section 9.2, in order to configure the FPGA after Linux Console boot, two files are required. FPGA device tree overlay (fpga.dtbo) and the FPGA configuration bitstream (soc_system.rbf).  I understand how to obtain the soc_system.rbf.  Section 9.2 also mentions issuing the following command:  dtc -O dtb -o fpga.dtbo -b 0 -@ fpga.dts  I copied the fpga.dts from the DE10_Standard_GHRD example, but for my own FPGA configuration how do I generate the fpga.dts. I think it is different from generating a soc_system.dts with sopc2dts (or is it!??!). Also, why is it that a device tree blob overlay(.dtbo) is needed instead of a .dts?  Thanks, Raul

[Altera_Forum]

Hi Anand, 

 When I read the DE10-Standard_User_manual.pdf, Section 9.2, there is mention about requiring 2 files in order to configure the FPGA after booting up with the Linux Console. The two files are fpga.dtbo and soc_system.rbf.  I do understand how to generate the soc_system.rbf file using the sof_to_rbf.bat file.  However, for generating the fpga.dtbo, the document mentions using the following command:  dtc -O dtb -o fpga.dtbo -b 0 -@ fpga.dts  This will create a device tree overlay (aka .dtbo) and it uses the fpga.dts as the input. The fpga.dts doesn't appear to be a regular dts file because after its header, it contains the following text:   /dts-v1/ /plugin/;   In addition, the fpga.dts file contains entries for led_fpga0-9, which cannot be found in the soc_system.dts.  I'm having trouble understanding what generates the fpga.dts because it looks like I'll need it in order to control LEDs and use switches and buttons since the soc_system.dts doesn't contain that kind of information.  Thanks, Raul

[Altera_Forum]

Hi Anand, 

 When I read the DE10-Standard_User_manual.pdf, Section 9.2, there is mention about requiring 2 files in order to configure the FPGA after booting up with the Linux Console. The two files are fpga.dtbo and soc_system.rbf.  I do understand how to generate the soc_system.rbf file using the sof_to_rbf.bat file.  However, for generating the fpga.dtbo, the document mentions using the following command:  dtc -O dtb -o fpga.dtbo -b 0 -@ fpga.dts  This will create a device tree overlay (aka .dtbo) and it uses the fpga.dts as the input. The fpga.dts doesn't appear to be a regular dts file because after its header, it contains the following text:   /dts-v1/ /plugin/;   In addition, the fpga.dts file contains entries for led_fpga0-9, which cannot be found in the soc_system.dts.  I'm having trouble understanding what generates the fpga.dts because it looks like I'll need it in order to control LEDs and use switches and buttons since the soc_system.dts doesn't contain that kind of information.  Thanks, Raul

[Altera_Forum]

--- Quote Start ---   I'm having trouble understanding what generates the fpga.dts because it looks like I'll need it in order to control LEDs and use switches and buttons since the soc_system.dts doesn't contain that kind of information.   --- Quote End ---    How you have designed Qsys or what all components are used?  Information from sopcinfo file are used to generate the device tree.  Refer below links. https://rocketboards.org/foswiki/documentation/gsrdv141devicetreegenerator https://rocketboards.org/foswiki/documentation/gsrd131devicetreegenerator https://www.alteraforum.com/forum/attachment.php?attachmentid=15039 https://www.alteraforum.com/forum/attachment.php?attachmentid=15040  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

Hi Anand, 

 I was able to run the dtc program where the input is a dtb file and the output is a dts file. From there I can get some clues about what was part of the dts. What I learned from my correspondence with Terasic support is that Qsys by itself doesn't generate everything needed for a device tree. One or more board files are part of the equation, too. For example, every time I loaded Linux Console to my DE10-Standard board, I noticed that i2c0-mux was present under /sys/class/leds. However, using the board files that came with my DE10-Standard board and the sopcinfo from a project, i2c0-mux was never present in /sys/class/leds.   I've now figured out how to edit my board files to include the i2c0-mux.  Thanks for the links. I will review them.  Regards, Raul

[greenlantern01]

Hi Raul,

Kindly share if you still have, the links you referred to, or any other information medium you used, to learn to edit the dts files according to your qsys. 

Thanks