I am designing a PCIe Card with Arria 10 FPGA. I also have an external 16bit parallel NOR FLASH to hold the configuration image.

[MServ4]

I am designing a PCIe Card with Arria 10 FPGA. I also have an external 16-bit parallel NOR FLASH to hold the configuration image. During system power-up, I am unable to get the FPGA completes its configuration via FLASH before the Root-Complex de-assert the PCIe RESET. Any solution?

[SreekumarR_G_Intel]

yes , it is possible via CvP (Configuration via protocol IP )

Here is the link for your reference

https://www.intel.com/content/www/us/en/programmable/documentation/dsu1441819344145.html

Thank you,

Regards,

Sree

[MServ4]

Thanks.

Do you know how to place the FPGA image into the serial FLASH (SPI FLASH)?

[SreekumarR_G_Intel]

yes....In the design you have to add the "Intel FPGA serial Flash loader IP core and ASMII ip core " Then using JTAG (USB blaster) you can directly load the FPGA image into the flash .

Here is the link from intel application notes

https://www.intel.com/content/www/us/en/programmable/documentation/mwh1410805299012.html

Also make sure you select the right serial flash device which is recommended by the Intel . List of supported device given below

https://www.intel.in/content/www/in/en/products/programmable/configuration-device.html

Thank you ,

Regards,

Sree