I am running a Signal Integrity simulation for PCIe Gen2 using Intel E3845 Processor. How do i use the FASE Verilog-A model provided? I am using HyperLynx VX.2.3 for my simulation. Please help. Thank you!!

[KeenYewL_Intel]

Hi users, I think you might have posted this thread into the wrong community forum. This forum only covers Intel FPGA product. Our agents can only help to provide assistance with regards to FPGA product. If you have further enquiries on other Intel product, please post your question to the correct Intel Community topics from the link below: https://forums.intel.com/s/ We will then require deleting this thread from the Intel FPGA forum topic. Thank you. Regards, KeenYew