I designed an FSM, and it's going to states that it shouldn't be able to go to. Please help me understand what my Verilog code is doing.

[NFerg1]

I am designing a Manchester receiver. The design simulates in modelsim. I synthesized the code and downloaded it to a de10 nano cyclone V fpga to test it, and I used Intel/Altera's signal tap logic analyzer tool to analyze the signals. I observed this strange error occur once. I'm really confused and curious. My state machine transitions from state 4 to 13, but state 4 can only transition to states 15, 9, or 5. How is this possible? I have posted the code for state 4 below, and a screenshot of the logic analyzer result. Any and all help/advice/criticism would be very much welcome.

Thanks!

[Vicky1]

Hi Nicholas,

Please provide screenshot of state machine viewer like attached.

=> 'Tool' -> 'Netlist Viewers' -> 'State Machine Viewer'

Regards,

Vikas

[sstrell]

Without seeing your state transition code, it's difficult to figure this out. Decimal 13 is binary 1101, so maybe the most significant bit of your state register is getting set somehow when you want to be going to state 5 (0101).