I'm having problems using signalTap with virtual jtag.

[KLohr]

I've ported a design using the virtual jtag IP which creates a virtual Uart on a max 10 device. I've done simpler designs that work with signaltap, but this one doesn't. As soon as I enable communication back to the host I can't use signal tap anymore? Any ideas?

[Kenny_Tan]

Hi,

Did you try the design in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_virtualjtag.pdf page 28? Did your design have a timing closed?

Also, there are example with the terasic on the virtual uart, you can refer to here https://nhiphanlogic.wordpress.com/2014/07/05/virtual-uart-for-the-terasic-de0-nano/

Thanks,

Best regards,

Kenny Tan

[KLohr]

The design I'm using is the virtual uart you referenced above. I've ported it over to the MAX10 because it was originally on cyclone. And yes, the timing is closed. The problem with signal_tap only starts once I open the telnet window and start echoing characters to the screen. I wonder if the polling loop in the tcl code is taking all the bandwidth and this isn't allowing signal_tap to run? I need to do more research into this and my final application isn't a uart, from a telnet window, so I'll move down that road and update this post if I get any results

[Kenny_Tan]

Did you use the fixed version as mention in the terasic example? https://github.com/binary-logic/vj-uart/commit/bdfd6772da6f92f6a9fc9836057b2bf896e4789d#diff-d41d8cd98f00b204e9800998ecf8427e

You can your question over there since this is terasic design and they are more familiarize with it.

[Kenny_Tan]

Is there any update?

[KLohr]

Thanks for checking up on me KTan9! We had to ship evaluation units this week, but hope to get back to the vjtag stuff next week. I'll let you know the results. My application is going to be completely tcl based that will kick off a calibration process in the FPGA that will output several thousand ADC values.

[Kenny_Tan]

Sure, let me know how it goes.

[Kenny_Tan]

Is there any update?

[KLohr]

Hi, I finally got back on this section of the fpga. I still get Unexpected JTAG communication error in signaltap when I run my tcl script. There is no problem if I simply write the VJTAG with a value and read one value back. It's only when I instantiate a wait loop that is continually reading the VJTAG that it causes the signaltap problem. I've attached my tcl script if it's any help.

[KLohr]

Well, I figured it out this morning. It's the device_lock -timeout 10000 command at the beginning of the tcl script. I copied that from the virtual jtag uart tcl script and it should only be at the beginning of any virtual_ir_shift/dr_shift pair and there should always be a device_unlock after that pair. The jtag uart tcl script had it at the beginning of the program and one at the end which locked out any other jtag access (including signal tap).