entity RisingEdge_DFlipFlop_AsyncResetLow is
Q : out std_logic;
Clk :in std_logic;
sync_reset: in std_logic;
D :in std_logic
architecture Behavioral of RisingEdge_DFlipFlop_AsyncResetLow is
Q <= '0';
Q <= D;
You have to be more clear on your requirements.
Question and implementation are different, in question you have mentioned "active high synchronous rest" and in code "AsyncResetLow". However your design is correct as per Asynchronous Reset Low.
For reference go to the template provided in quartus under edit->insert template->VHDL->Full designs->Shift Register.
process (clk, reset,enable_n ) begin if (reset = '1') then --Active high Asynchronous rest elsif (rising_edge(clk)) then if (enable_n = '0') then --Active low synchronous enable end if; end if; end process;
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.