I used Quartus to generate the soc_system.sopcinfo file, and then use sopc2dts to build the corresponding soc_system.dtb. It seems that everything work fine except that the eth0 is down. Anyone have similar problem or any suggestion?

[Fawaz_Al-Jubori]

Hello,

May I know which FPGA device are you referring to? is it development kit or custom board?

thank you

[wchen50]

I am using DE0-Nano-Soc development board, which is using Cyclone V.

[Fawaz_Al-Jubori]

Hello.

Can you share with me the device tree?

Furthermore, have you tried the default GHRD image came with the board?

Thank you