FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5914 Discussions

I used Quartus to generate the soc_system.sopcinfo file, and then use sopc2dts to build the corresponding soc_system.dtb. It seems that everything work fine except that the eth0 is down. Anyone have similar problem or any suggestion?

wchen50
Beginner
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Fawaz_Al-Jubori
Employee
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Hello,

May I know which FPGA device are you referring to? is it development kit or custom board?

 

thank you

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wchen50
Beginner
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I am using DE0-Nano-Soc development board, which is using Cyclone V.

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Fawaz_Al-Jubori
Employee
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Hello.

Can you share with me the device tree?

Furthermore, have you tried the default GHRD image came with the board?

 

Thank you

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