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Idaville LCC I2C layout trace length

LisaXu
Beginner
659 Views

Dear Intel Team:

we checked the document <Idaville LCC Platform Design Guide (PDG)>, it shows I2C/SMBUS PCB trace length should be kept in below 30 inch. 

In my opinion, we ususally use ~3pF/inch for I2C trace length calculation, and 30inch just 90pF, it is highly below I2C standard mode/Fast mode 400pF, So could you share why you define the 30 inch PCB trace length restrict? 

Thanks!

Best Regards

Lisa

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AqidAyman_Intel
Employee
371 Views

Hi Lisa,


I have got input from the internal team as below:


All these recommendations in the tables in section 13.1.2 were put together using simulations by our Signal Integrity Team.


I checked for example the guidelines provided in the Whitley PDG (doc# 574174). Whitley is the platform for ICX-SP, which has a different PCH than ICX-D. Checking table 6-36 in the Whitley PDG I see similar number to the table 13-1 in the Idaville PDG. It seems that even with a different PCH they arrived at similar conclusions.


You also can run your own simulations and if you think the board is able to handle longer traces, they can do it, but Intel can’t offer support if they deviate from our recommendations.


Regards,

Aqid


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AqidAyman_Intel
Employee
593 Views

Hi Lisa,


Can you share which page it is? I may need to consult the internal team who owned the documentation.


Regards,

Aqid


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LisaXu
Beginner
578 Views

Hi Aqid:

Item 13.1.2 on Page 567 & 568 of document <Idaville LCC Platform Design Guide(PDG) Revision 2.4 November 2023>.

LisaXu_0-1716801510854.png

LisaXu_1-1716801646336.png

 

Best Regards

Lisa

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AqidAyman_Intel
Employee
538 Views

Hi Lisa,


Okay noted on this. Thank you for the confirmation. I will update you back once I got any input from the internal team who owned the documentation.


Regards,

Aqid


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LisaXu
Beginner
484 Views

Hi Aqid:

Thanks for your kindly support, we are doing review for PCB trace length. we need your reply to determine need add repeater or not.

Best Regards

Lisa

 

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sstrell
Honored Contributor III
427 Views

I feel like this post is getting "Platform Design" confused with the "Platform Designer" tool found in Quartus since this doesn't sound like it has anything to do with FPGAs.

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LisaXu
Beginner
411 Views

Hi Sstrell:

Aqid is helping asking Intel internal team for reply, And I have transferred from other forum,they told me should post in this forum.

Or I donot which forum should I post and It will waste too much time.

Best Regards

Lisa

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AqidAyman_Intel
Employee
372 Views

Hi Lisa,


I have got input from the internal team as below:


All these recommendations in the tables in section 13.1.2 were put together using simulations by our Signal Integrity Team.


I checked for example the guidelines provided in the Whitley PDG (doc# 574174). Whitley is the platform for ICX-SP, which has a different PCH than ICX-D. Checking table 6-36 in the Whitley PDG I see similar number to the table 13-1 in the Idaville PDG. It seems that even with a different PCH they arrived at similar conclusions.


You also can run your own simulations and if you think the board is able to handle longer traces, they can do it, but Intel can’t offer support if they deviate from our recommendations.


Regards,

Aqid


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LisaXu
Beginner
356 Views

Hi Aqid:

Thanks for your great supports

Best Regards

Lisa

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AqidAyman_Intel
Employee
333 Views

Hi Lisa,


No worries! Happy to help you.

I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.


Regards,

Aqid


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