If you configured DDR4 IP with 64 DQ data width, then at one clock cycle, you can transfer max 128 bits data due to double data rate (DDR) architecture.
DDR architecture works in a way where it will utilize both rising edge of clock and falling edge of clock to transfer data.
- Meaning at clock rising edge, you transfer 64 bits
- At the same clock falling edge. you transfer another 64 bits
- That's why in one clock that contains both rising edge and falling edge, you get total of 128 bits transfer
I hope I clear your doubt.