If there is a delay on the clock, will it affect LVDS reception?

[TGao]

Hi

We're going to add a buffer to the clock pair on the circuit，I'm not sure if it can affect the lvds reception?

Ted.Gao

[jhold7]

hi

any of the PLL outputs through a global buffer (BUFG), and the ... LVDS Clock P ... complement signals are fed through master and slave input delays (both ... reception of data but does affect the current position of the sample ..

[Rahul_S_Intel1]

Hi,

Are you refereing to internal buffer or external buffer to FPGA

[TGao]

Hi EahulS, There are no internal buffer in CIV, and no external buffer.

[Rahul_S_Intel1]

Hi ,

In cyclone IV there is buffer .

[Rahul_S_Intel1]

Hi ,

Kindly let me know if you need further assistance

[TGao]

Hi Rahuls，

No more questions, Thanks

Ted

[Rahul_S_Intel1]

Hi ,

 Really glad to know .

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