FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5234 Discussions

If there is a delay on the clock, will it affect LVDS reception?

TGao
Beginner
271 Views

Hi

We're going to add a buffer to the clock pair on the circuit,I'm not sure if it can affect the lvds reception?

 

Ted.Gao

0 Kudos
7 Replies
jhold7
Beginner
211 Views

hi

any of the PLL outputs through a global buffer (BUFG), and the ... LVDS Clock P ... complement signals are fed through master and slave input delays (both ... reception of data but does affect the current position of the sample ..

Rahul_S_Intel1
Employee
211 Views

Hi,

 

Are you refereing to internal buffer or external buffer to FPGA

TGao
Beginner
211 Views
Hi EahulS, There are no internal buffer in CIV, and no external buffer.
Rahul_S_Intel1
Employee
211 Views

Hi ,

In cyclone IV there is buffer .

Rahul_S_Intel1
Employee
211 Views

Hi ,

Kindly let me know if you need further assistance

TGao
Beginner
211 Views

Hi Rahuls,

No more questions, Thanks

 

Ted

Rahul_S_Intel1
Employee
211 Views

Hi ,

 

 Really glad to know .

 

------------------------------------------------------------------------------------------------------------

 

Don't forget to click on Select as Best answer

 

---------------------------------------------------------------------------------------------------------

Reply