I am currently designing a delay chain using Cyclone V and come across a strange problem.
The design in verilog is shown below:
input wire delay_in;
output wire delay_out;
To prevent compiler from ignoring them during synthesis, my setting is shown in the attachment file.
Though I turned off all buffers', including soft ones, optimization choices, the post-mapping and post-fitting viewer still do not show my design. More confusing thing is the RTL Viewer indeed shows that my design module exists.
During the placement and fitting stage, Quartus generates warning that my module does not exist, which means it is some how ignored by the compiler. (Warning (15706): Node "delay_detection:UUT|delay_chain:delay_DUT" is assigned to location or region, but does not exist in design)
Does anyone know why this the case? If this issue cannot be solved by the compiler's settings, could anyone recommend a way of cascading four logic units? (I have tried AND, Or and ordinary buffers, but all failed. I do not want to use adder chain, as I want to know the minimum resolution of a logic gate in the cyclone V.)
Thank you very much!
Thank you so much for your help!
May I ask the test case here you refer to is simulation or real test on board?
If it is simulation, I have done RTL simulation using Modelsim, but does not show any effect on delay. (I guess this is due to failure of low level simulation in modelsim)
The software edition is Quartus Lite 19.1, do you think the Lite Edition is not that smart to map the code into the hardware?
You have mentioned the software issues Warning (15706): Node "delay_detection:UUT|delay_chain:delay_DUT" is assigned to location or region, but does not exist in design) during the compilation. I would like to check if this is being optimized away during the compilation. Could you share the design.qar and testbench file for investigation? To generate the file, click on Project > Archive Project > Archive.
The buffers in the delay_chain are optimized by the software. You have to use keep synthesis attribute to prevent the software from minimizing or removing the buffer.
You may refer to the synta here:
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Below is the HDL that works
input wire delay_in;
output wire delay_out /* synthesis keep*/;
wire buff /* synthesis keep*/;
wire buff2/* synthesis keep*/;
wire buff3/* synthesis keep*/;
assign delay_out = buff3;
assign buff3 = buff2;
assign buff2 = buff;
assign buff = delay_in;