FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
6020 Discussions

Im using de10-lite fpga board, the spec says it has a one chip sdram with 32M address, but it only has 13bit address and 2bit bank address select, wich brings me to 64K address. can anyone help me understand what am missing, how do I access the whole 64M?

0 Kudos
1 Reply

Hi sir,

You are using Terasic board, it is better if you can check with Terasic directly.


but let me try to help here:

Look like you calculate the density with formula = 2^13 * 2 ^2 and you get 32k?

For DRAM, the correct density calculation as below:

2^(row addressing) * 2^(column addressing) * 2^(bank addressing)

to get all the addressing bit as below, you have to check the DRAM datasheet.


Any, I guess the DRAM that you using have address as below:

2^13 * 2^11 * 2^2

= 8k * 2k * 4



note: column addressing is a subset of row addressing.


try to get an example of DRAM datasheet, check table 2: addressing and you will understand clearer.


0 Kudos