I'm using a Cyclone II Starter Kit to control a piece of equipment. We use almost all of the I/O lines on the HMSC connector for output. The control for the equipment is implemented in a block diagram, with specific timing information residing in ALTSYNCRAM defined as being able to be accessed by the In-System Memor Content Editor. So the user can load timings from a PC File, using the In-System Memory Content Editor, and then they activate the control logic sequence. Seems to work fine, and we're pretty please to get control of 60 I/Os for $300 in hardware and a few days programming effort! Except:Now the users want to have a LabView program on the PC generate the timing file, and automatically download the file to the FPGA and write it into memory, a function that Quartus/In System Memory Content Editor doesn't appear to support. Any suggestions how I can "easily" allow an PC program to push a .MIF or .HEX file (100 16bit words) to the FPGA on a Cyclone Starter Kit board? Or otherwise push data into a Starter Kit FPGA memory location? I'm wondering if the API that the In-system Memory Content Editor is available, or if there's tools to allow us to emulate that interface. Thanks, Tony
Basically, there is a comfortable way to access the In-System-Memory-Instances through the Virtual JTAG protocol. altsource_probe_body.vhd shows the specific part, the general part is documented in the Virtual JTAG Megafunction User Guide. Unfortunately, no documented interface yet exists in the Quartus software stack, although sld_hapi.dll apparently has the required functionality.