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Increase frequency of HPSGPIO

snehal_p
New Contributor I
3,360 Views

Hello,

How can we increase the HPS gpio frequency?

I'm driving Shift register CD4094 from HPS. Can I increase the frequency of clk generated from hps to drive cd4094? what is the maximum frequency generated .

 

Thanks,

snehal_p

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1 Solution
aikeu
Employee
3,078 Views

Hi snehal_p,


I try to check further regarding the gpio limitation on arm cortex a9 for the HPS.

It shows that:

"The PL061 PrimeCell General Purpose Input/Output (GPIO) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. Use the GPIO to generate or detect low frequency signals (less than 1MHz)."

https://developer.arm.com/documentation/dui0440/b/programmer-s-reference/general-purpose-input-output--gpio

It seems that the frequency you are capable of generating also meet around that range due to the limitation of the GPIO regardless of the instruction cycles which involves in the gpio toggling operation.


Thanks.

Regards,

Aik Eu


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19 Replies
aikeu
Employee
3,314 Views

Hi snehal_p,


May I know you are referring to which dev kit board in particular?


Thanks.

Regards,

Aik Eu


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snehal_p
New Contributor I
3,305 Views

Hi Aik Eu,

It is a Cyclone V customized board. We are driving LCD from HPS, serial data is converted to parallel  by shift register CD4094.

PFA block diagram.

We want to increase the data clk frequency.

Can we increase the hps gpio frequency.

Thanks,

snehal_p

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aikeu
Employee
3,297 Views

Hi snehal_p,


Do you mean you are using the HPS GPIO to drive the clock of your Cd4094 shift register IC?


Thanks.

Regards,

Aik Eu


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snehal_p
New Contributor I
3,294 Views

Hello Aikeu,

 

Yes we are using hps gpio to drive the clock of shift register.

 

Thanks,

snehal_p

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aikeu
Employee
3,270 Views

Hi snehal_p,


Are you trying to set the GPIO example from low -> high then high -> low continuously to function as a clock to the Shift register?

If that is the case the fastest time achievable will based on the instruction cycle of the HPS system. Meaning the time it takes for one single instruction to set a GPIO pin to high/low . You can only set the period of your generated clock slower than your system clock but not faster than that.


Thanks.

Regards,

Aik Eu


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snehal_p
New Contributor I
3,261 Views

Hello Aik Eu,

 

Yes, system clock is 50 Mhz.

 

Thanks,

snehal_p

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aikeu
Employee
3,246 Views

Hi snehal_p,


Are you using the PIO IP on the FPGA side to drive the clock of the shift register? if so then can consider increase 50 Mhz and see if it helps and do not affect the overal system design clock synchronization.

The HPS processor operating frequency for Cyclone V is 925 Mhz and can check in platform designer on the HPS IP block under Output clocks.


Thanks.

Regards,

Aik Eu


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snehal_p
New Contributor I
3,237 Views

Hello Aik Eu,

 

No, we are not using PIO IP, actually the clk is connected to the hpsgpio on the board.

Is there any way we can increase the clock frequency to drive the shift register to 10-14MHz.

What is the maximum frequency that could be achieved on hpsgpio of my system clock is 50 Mhz.

 

Thanks,

snehal_p

 

 

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aikeu
Employee
3,191 Views

Hi snehal_p


The HPS processor frequency clock 925Mhz will determine it's instruction cycle speed thus it should have no problem working with 10-14Mhz for the shift register if not relying on the system clock source.

If your gpio is relying on the system clock source and still within the 50Mhz of the system clock, then it should be fine to achieve that. The max will be 50Mhz for your shift register based on the default setting of the clock source unless you increase it.


Thanks.

Regards,

Aik Eu


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snehal_p
New Contributor I
3,183 Views
Hello Aik Eu,
Thanks for your response.
Can you please help on how to increase the frequency as now we get frequency around 900Khz for shift register
PFA c code .
Thanks,
snehal_p
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snehal_p
New Contributor I
3,181 Views

Hello,

PFA code.

Thanks,

snehal_p

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aikeu
Employee
3,164 Views

Hi snehal_p,


If I am correct for the below:

It seems that each time you write the 8 bit data to the shift register, you will trigger a clock signal(DISP_HMI_CLK) to let the shift register for acknowlege a single bit of data at the data line of the shift register.

The clock is generated based on how the code is written in instruction sequence considering the time taken for the function to perform the shift operation.


May I know is the shift operation eventually able to display the logo image from the code without issue?

If no issue what is the problem that you are observing from the operation to have image display on the LCD?

May I know how you get to measure the clock signal in the first place?

I suggest to tap the clock signal of the shift register wher you can observe the time take for 8 bit data transfer to the shift register

I cant tell how fast is the clock signal from the code itself. If the current clock frequency is too high, higher than the expected 900khz which you prefer to have, then you can put delay in the between instruction to fine tune it.


Thanks.

Regards,

Aik Eu


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snehal_p
New Contributor I
3,144 Views

Hello Aik Eu,

Yes we are able to get images on display.
We have a requirement of higher frequency so it will provide higher fps.

We measured the clock frequency by probing the  DISP_HMI_CLK on oscilloscope.
900khz is one cycle of 1bit data on disp-hmi-clk, we need to increase it to 10MHz.

PFA hps clock setting.

 

Thanks,

snehal_p

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aikeu
Employee
3,139 Views

Hi snehal_p,


The signal behaviour is different from how I expected. It seems that each instruction cycle a lot slower than I thought.


Can share with me the oscilloscope actual results of the data and clock signal when sending the 8bit transter to the shift register?

Another thing to try is just by sending the clock signal example like below:

while(1)

(

  alt_setbits_word( COMMON_TEXT_FOR_GPIO0, DISP_HMI_CLK );


  alt_clrbits_word( COMMON_TEXT_FOR_GPIO0, DISP_HMI_CLK );

};

How the above gpio signal frequency clock will look like from the oscilloscope.


Thanks.

Regards,

Aik Eu


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snehal_p
New Contributor I
3,129 Views

Hello Aik Eu,

 

PFA oscilloscope images and code screenshot.

AI_CLK_PIN in the code is continuous clock signal.  

 

Thanks,

snehal_p

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aikeu
Employee
3,079 Views

Hi snehal_p,


I try to check further regarding the gpio limitation on arm cortex a9 for the HPS.

It shows that:

"The PL061 PrimeCell General Purpose Input/Output (GPIO) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited. Use the GPIO to generate or detect low frequency signals (less than 1MHz)."

https://developer.arm.com/documentation/dui0440/b/programmer-s-reference/general-purpose-input-output--gpio

It seems that the frequency you are capable of generating also meet around that range due to the limitation of the GPIO regardless of the instruction cycles which involves in the gpio toggling operation.


Thanks.

Regards,

Aik Eu


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snehal_p
New Contributor I
3,072 Views

Hello Aik Eu,

 

Thanks for the support.

Can you also help me with design example to use HPSGPI as interrupt, we could configure HPSGPI it as interrupt but could not understand how to use it.

 

Thanks,

snehal_p

 

 

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aikeu
Employee
3,034 Views

Hi snehal_p,


I’m glad that your initial question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Anyway feel free to provide a good survey feedback if receive any. Thank you!


Thanks.

Regards,

Aik Eu


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snehal_p
New Contributor I
2,999 Views
Hello Aik Eu,
Below is the link to the HPSGPI interrupt thread, Can you please help with this topic.
community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-to-configure-and-use-HPSGPI-pin-as-interuppt/m-p/1478175#M24671

Thanks,
snehal_p
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