Inquiry Regarding MAX 10 FPGA Power Management

[MartinMaa]

Dear Intel Technical Support Team,

I am currently working with the MAX 10 FPGA and have a question related to power management. Specifically, I would like to understand the power requirements for unused I/O and their associated power banks.

A. For unused I/O, do I need to connect power to their respective power banks?
B. If not, what considerations should I keep in mind when configuring the power for unused I/O?
Your guidance on this matter would be greatly appreciated. Thank you in advance for your assistance.

Martin.

[MartinMaa]

Hi, can anyone assist me? Because my board is too small, I have to reduce many passive components.

[MartinMaa]

I am not using these I/O pins. Can I remove these resistors and capacitors to make VCCIO non-connected.

Thanks.

[Ash_R_Intel · Accepted solution]

Hi,

Based on this Knowledge Article Is it necessary to power all the VCCIO IO Banks on a MAX 10 device... (intel.com), it is recommended to power-up all the VCCIO rails even when not used.

However, you may choose to connect to the power rails to minimum required power mentioned in the datasheet, like 1.0V. Single Supply Devices Power Supplies Recommended Operating Conditions (intel.com)

Regards

[Ash_R_Intel]

Hi,

I am glad that you accepted the solution that I provided earlier. Hence, setting this case to closure. However, it will still be open for the community members to comment on.

Regards