Community
cancel
Showing results for 
Search instead for 
Did you mean: 
leondietrich
Beginner
247 Views

Intel Agilex F-Series dev kit cant be programmed by JTAG

Hi,
Im officially out of luck. After wasting an entire week on trying to get the programmer to work I posting my question within this forum.

I've got multiple bit stream files I'd like to use for configuration of our agilex FPGA (AGFB014R24A2E3VR0). While the UBII and Power Max 10 chips do seam to work (the board test system shows power and clock stats) the programming (both our bitstream and the intel example bitstreams) always fails at 13% (using both the quartus programmer and the one provided by the BTS). Searching the exact error message (obtained by right click -> copy on the log message) wasn't of any help. We're using Quartus Pro 20.4 on Ubuntu 20 and Windows 10 (neither worked, both with the same issue).

Please review the attached screen shot for further details.

0 Kudos
11 Replies
YuanLi_S_Intel
Employee
229 Views

Hi

 

 

I suspect your TCK frequency might be the root cause here.

 

Can you kindly try to reduce your TCK frequency to 6 MHz (default value)?

Below link is the command to change TCK frequency (on page 14= "2.8. Changing the TCK Frequency")

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr_ii_cable.pd...

 

Kindly try it out with your design and let me know the result.

 

Thanks


leondietrich
Beginner
227 Views

Hi, thanks for your answer. We already tried 1MHz, 6MHz, 12MHz, 24MHz both by changing it within the GUI and the command line tools (al dough we didn't tried 12MHz on Ubuntu). Unfortunately none of these combinations worked.
YuanLi_S_Intel
Employee
199 Views

Hi,


Can you check the following?

  • Have you tried to program the agilex with a simple design with SOF bitstream?


Thank You


leondietrich
Beginner
181 Views

Hi, Thanks for your help! We've also tried to configure the FPGA with an SOF bitstream, reassembling a fairly simple (a 4 bit shift register enabling one QSFP and GPIO led at a time, powered by a clock divider in order to make the blinking human visible, the HDL code itself is known to be working). We've also tried the sof bitstreams provided by the example projects. None of those worked either.
leondietrich
Beginner
177 Views

I don't know if it's relevant but we're getting the following warning when trying to program said test-bitstream (which I've attached to this message for reference purposes):

Warning(19729): Current CMF data structure hash (0x15CD440C) is older version than latest CMF data structure but still allowable.
This might be transition period. You should update your CMF to latest version with hash { 0x8AC9CBBA } [ACDS 20.4 Release]

YuanLi_S_Intel
Employee
120 Views

Hi,


May i know which SOF bitstream you are using in the design example? Can you create a simple SOF file with simple input and output initialization and program and see?


Meanwhile for the warning message regarding to CMF, it can be safely ignored.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/compon...


Thank You.


Regards,

bruce


leondietrich
Beginner
113 Views

Hi,

from the BTS we've tried bts_config.sof and qsfpdd_xcvr_nrz_25gbps.sof as well as the GPIO example. The Bitstream we've provided above (Have a look inside Hello_World.tar.xz), initializes the I/O and toggles the GPIO and QSFP leds at 1Hz. Besides writing a bitstream generated by the golden top example, I'm out of Ideas what could be more simple.

Also I observed that sometimes, the first JTAG timeout error message occures prior to the 209060 message indicating the start of the programming process.

YuanLi_S_Intel
Employee
106 Views

Hi,


Can you share me the screenshot of the Quartus programmer?


Also, what is the device part number used in the quartus design?


Thank You.


Regards,

Bruce


leondietrich
Beginner
44 Views

We're using the AGFB014R24A2E3VR0 part as stated on the sticker on our dev kit. Since our last post we downgraded to Quartus 19.1 and get a different error since then (Error(18952): Error status: Synchronization failed). I've attached a recent screenshot as requested.

remmina_Schnellverbindung_202133-92756,514732.png

 

YuanLi_S_Intel
Employee
29 Views

Can you try to use the previous programmer version that you are using? Also, try to remove the other devices in the JTAG chain and remain only the agilex.


leondietrich
Beginner
27 Views

Hi, Do you mean Quartus 20 with "previous programmer version"? Also, according to the documentation provided by Intel the second device in the chain (the MAX 10 fpga) can't be removed from the chain. All other available DIP switches only add further devices to the JTAG chain.