Solved: Intel Agilex F-Series dev kit cant be programmed by JTAG

leondietrich · ‎02-09-2021

Hi,
Im officially out of luck. After wasting an entire week on trying to get the programmer to work I posting my question within this forum.

I've got multiple bit stream files I'd like to use for configuration of our agilex FPGA (AGFB014R24A2E3VR0). While the UBII and Power Max 10 chips do seam to work (the board test system shows power and clock stats) the programming (both our bitstream and the intel example bitstreams) always fails at 13% (using both the quartus programmer and the one provided by the BTS). Searching the exact error message (obtained by right click -> copy on the log message) wasn't of any help. We're using Quartus Pro 20.4 on Ubuntu 20 and Windows 10 (neither worked, both with the same issue).

Please review the attached screen shot for further details.

leondietrich · ‎03-29-2021

Hi,

thanks a lot for your help! We've fixed this issue now. One thing we'd like to share, for a potential future reader, is that in addition to the above mentioned article one needs to completely erase the flash prior to configuring. Our working solutions looks like the following:

Power off the board. Waiting for the caps to be drained doesn't seam to be necessary.
Set MSEL[2:0] to ON/OFF/OFF
Power on the board.
Erase the boards flash using the programmer tools
Power off the board.
Set MSEL[2:0] to OFF/OFF/OFF
Power on the board
Programm your *.sof file.

It's also required to leave the JTAG chain in the default configuration while erasing the flash. Last but not least: If step 8 fails retry a couple of times until it stops failing (we usually don't need more than 3 tries). It also seams to be more reliable (programming fails less often) at 24MHz than 6MHz, which the programmer defaults to anyway.

View solution in original post

YuanLi_S_Intel · ‎02-10-2021

Hi

I suspect your TCK frequency might be the root cause here.

Can you kindly try to reduce your TCK frequency to 6 MHz (default value)?

Below link is the command to change TCK frequency (on page 14= "2.8. Changing the TCK Frequency")

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr_ii_cable.pd...

Kindly try it out with your design and let me know the result.

Thanks

leondietrich · ‎02-10-2021

Hi, thanks for your answer. We already tried 1MHz, 6MHz, 12MHz, 24MHz both by changing it within the GUI and the command line tools (al dough we didn't tried 12MHz on Ubuntu). Unfortunately none of these combinations worked.

YuanLi_S_Intel · ‎02-10-2021

Hi,

Can you check the following?

Have you tried to program the agilex with a simple design with SOF bitstream?

Thank You

leondietrich · ‎02-11-2021

Hi, Thanks for your help! We've also tried to configure the FPGA with an SOF bitstream, reassembling a fairly simple (a 4 bit shift register enabling one QSFP and GPIO led at a time, powered by a clock divider in order to make the blinking human visible, the HDL code itself is known to be working). We've also tried the sof bitstreams provided by the example projects. None of those worked either.

leondietrich · ‎02-11-2021

I don't know if it's relevant but we're getting the following warning when trying to program said test-bitstream (which I've attached to this message for reference purposes):

Warning(19729): Current CMF data structure hash (0x15CD440C) is older version than latest CMF data structure but still allowable.
This might be transition period. You should update your CMF to latest version with hash { 0x8AC9CBBA } [ACDS 20.4 Release]

dsigner · ‎03-08-2021

I observe the Warning(19729) as well.

Mengjie · ‎03-09-2021

It should have something to do with Quartus compatibility issue from 19.x to 20.4, which means you probably fail to configure FPGA SOF 20.x again if FPGA has been configured with 19.x image right after power cycle. For devkit, it usually has an image in ASx4 flash for power-on boot-up, so if the AS programming file JIC file generated by 19.x, then it probably runs into FPGA 20.x SOF file configuration issue later on after power cycle. So there are two options to go, one is to erase ASx4 flash with Programmer, the other one is to set MSEL to JTAG only mode. BTW, please do use 19.x Programmer to configure 19.x SOF file, same to 20.x SOF file, otherwise, it may run into configuration issue as well.

dsigner · ‎03-09-2021

I can confirm that setting SW1.1 to ON results in a successful load of the SOF after a power cycle.

Star · ‎06-22-2021

It seems your analysis is reasonable. I wonder how to erase ASx4 flash with Programmer before the FPGA can be configured. Are there any documents illustrate this operation?

YuanLi_S_Intel · ‎02-21-2021

Hi,

May i know which SOF bitstream you are using in the design example? Can you create a simple SOF file with simple input and output initialization and program and see?

Meanwhile for the warning message regarding to CMF, it can be safely ignored.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2020/warning--19729---current-cmf-data-structure-hash--0xa2c420ac--is0.html

Thank You.

Regards,

bruce

leondietrich · ‎02-22-2021

Hi,

from the BTS we've tried bts_config.sof and qsfpdd_xcvr_nrz_25gbps.sof as well as the GPIO example. The Bitstream we've provided above (Have a look inside Hello_World.tar.xz), initializes the I/O and toggles the GPIO and QSFP leds at 1Hz. Besides writing a bitstream generated by the golden top example, I'm out of Ideas what could be more simple.

Also I observed that sometimes, the first JTAG timeout error message occures prior to the 209060 message indicating the start of the programming process.

YuanLi_S_Intel · ‎02-24-2021

Hi,

Can you share me the screenshot of the Quartus programmer?

Also, what is the device part number used in the quartus design?

Thank You.

Regards,

Bruce

leondietrich · ‎03-03-2021

We're using the AGFB014R24A2E3VR0 part as stated on the sticker on our dev kit. Since our last post we downgraded to Quartus 19.1 and get a different error since then (Error(18952): Error status: Synchronization failed). I've attached a recent screenshot as requested.

YuanLi_S_Intel · ‎03-05-2021

Can you try to use the previous programmer version that you are using? Also, try to remove the other devices in the JTAG chain and remain only the agilex.

leondietrich · ‎03-05-2021

Hi, Do you mean Quartus 20 with "previous programmer version"? Also, according to the documentation provided by Intel the second device in the chain (the MAX 10 fpga) can't be removed from the chain. All other available DIP switches only add further devices to the JTAG chain.

dsigner · ‎03-08-2021

I'm observing the exact same problem on two (out of two) boards.

Our boards are based upon the AGFB014R24A2E2VR0 device.

The result is the same with a very simple LED flashing design as with a design downloaded from:

https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/agilex/f-fpga/agilexfb_agfb014r24a2e2vr0_fpga_en_reva_v20.4b72_v1.0.zip

For example:
agilexfb_agfb014r24a2e2vr0_fpga_en_reva_v20.4b72_v1.0/examples/pcie_gen4/pcie_gen4_ep_ed.sof

Setting DEVICE_INITIALIZATION_CLOCK INIT_INTOSC does not change the result.

It fails at different TCK speeds, including 6MHz.

Running thousands of IDCODE cycles reports no problems.

Using an external USB Blaster (TerASIC) results in the exact same error messages.

I'm running Quartus Programmer Pro v20.4.0.72 under Ubuntu 18.4

I have no problems loading a sof on a CycloneV SoC board using the same host and SW.

All DIP switches settings are as when the boards were received and according to the default values in the user guide at:
https://www.intel.com/content/www/us/en/programmable/documentation/zbg1567202330317.html

I always get the error:

Error (18950): Device has stopped receiving configuration data
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18947): Device not responding
Error (209012): Operation failed

the first time after power cycle of the board. Then any subsequent programming operations results in:

Error (18939): Unexpected error in JTAG server: Timeout
Error (18939): Unexpected error in JTAG server: Timeout
Error (18952): Error status: Synchronization failed
Error (209012): Operation failed

YuanLi_S_Intel · ‎03-15-2021

Hi Leon,

Can you try to change SW1.1 to ON as per suggested? Any update on this?

leondietrich · ‎03-15-2021

Hi,

I'll be in office tomorrow and will report my results here.

leondietrich · ‎03-16-2021

Hi, As requested I checked if setting SW1.1 to ON is improving anything. The only difference it made was that it's now failing consistently at 14% instead of 13%. It's still failing with the timeout error from the JTAG server.

YuanLi_S_Intel · ‎03-22-2021

Hi,

It seems like we have a solution for this error message (Error(18939): Unexpected error in JTAG server: Timeout.):

https://www.intel.la/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/component/2021/error-18939---unexpected-error-in-jtag-server--timeout-.html

Also, after that, can you change the TCK frequency to 6 MHz?