Intel® Core™ i3-12100, MSI delay

[Peter942]

Dear People

For a medical system we use an Intel® Core™ i3-12100 system with a specific FPGA card on PCIe slot1 (close to CPU). The card has a reference clocks and generate MSI interrupts.

We see on this system significant additional latency of >20us compared with e 10e generation CPU. That is the time that the interrupt is started to send by MSI and when the interrupt is receiving and start the interrupt handler on CPU side. We use Vxworks Realtime OS.

Before the interrupt is send the time is stored on FPGA card. When the CPU received the interrupts the time is requested from the FPGA card. Of course there are some time overhead on this.

Is there any information available about the timing or MSI message transport time before the interrupt is received on CPU level?

I can not found any good information in 325462-sdm-vol-1-2abcd-3abcd-4 (1).pdf

We use also a process to send data from FPGA (PCIe) to CPU memory by DMA started from FPGA side. How is the L1,l2,L3 cash synchronized when due external DMA the memory is updated and some parts is also in L-X cash? Result this in extra delay? Where can I found more information about this? 

[Jose_Intel]

Hello @Peter942

Thank you for posting on the Intel️® communities.

Please keep in mind that the corresponding team will contact you soon to help you with your request.

Best regards,

Jose B.

Intel Customer Support Technician

[wchiah]

Hi Peter,

Can I know what is the FPGA device that you currently using ?

Regards,

Wincent_Intel

[Peter942]

Wincent_intel

We use an Xilinx FPGA. We do now indept timings measurements by FPGA scope. The MSI interrupt is send by Xilinx software. I want to check tomorrow about the Xilinx type.  We found out that we lost 10us before the standard software block PCIe wrapper from Xilinx send the MSI interrupt. But still we see lot of delay variation between 5-15us before the interrupt handler is started. We have no detail what are the timings cost to start an interrupt function in the intel core. We have disable Hyperthreading and disable all power optimizations from the CPU. Also there is no extra graphic card in the system and only traffic to the LAN port is ongoing.  Is there any timing information about interrupthandling inside a CPU?

Is this for everyone visible? Otherwise I can send more details about the issue. 

Theon 

[wchiah]

Hi,

I wish to follow up with you about this case.

Any update from previous question ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

[wchiah]

Hi Peter,

First, based on early observation, this issue is seen as happening on the FPGA side.

Also more related to FPGA implementation.

On this forum page, we are supporting Intel/Altera FPGA devices.

I wish to help you with the issue you facing, but I am afraid I am not equipped with any Xilinx product knowledge.

I suggest you go to https://support.xilinx.com/s/topiccatalog?language=en_US

Do you still have any questions about Intel/Altera product?

Otherwise, I would like to have your permission to close this forum case .

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

[wchiah]

Hi

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

As per suggestion, we suggest you to go for Xilinx Fpga Support forum.

Hence, This thread will be transitioned to community support.

If you have a new question about Intel FPGA, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.